The Designer's Guide to the Cortex-M Processor Family

The Designer's Guide to the Cortex-M Processor Family

A Tutorial Approach

1st Edition - March 13, 2013

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  • Author: Trevor Martin
  • eBook ISBN: 9780080982991

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The Designer’s Guide to the Cortex-M Family is a tutorial-based book giving the key concepts required to develop programs in C with a Cortex M- based processor. The book begins with an overview of the Cortex- M family, giving architectural descriptions supported with practical examples, enabling the engineer to easily develop basic C programs to run on the Cortex- M0/M0+/M3 and M4. It then examines the more advanced features of the Cortex architecture such as memory protection, operating modes and dual stack operation. Once a firm grounding in the Cortex M processor has been established the book introduces the use of a small footprint RTOS and the CMSIS DSP library. With this book you will learn: The key differences between the Cortex M0/M0+/M3 and M4 How to write C programs to run on Cortex-M based processors How to make best use of the Coresight debug system How to do RTOS development The Cortex-M operating modes and memory protection Advanced software techniques that can be used on Cortex-M microcontrollers How to optimise DSP code for the cortex M4 and how to build real time DSP systems

Key Features

  • An Introduction to the Cortex microcontroller software interface standard (CMSIS), a common framework for all Cortex M- based microcontrollers
  • Coverage of the CMSIS DSP library for Cortex M3 and M4
  • An evaluation tool chain IDE and debugger which allows the accompanying example projects to be run in simulation on the PC or on low cost hardware


Embedded systems engineers, undergraduates and graduates developing embedded applications.

Table of Contents

  • Dedication




    About the Author

    Chapter 1. Introduction to the Cortex-M Processor Family

    Cortex Profiles


    Advanced Architectural Features




    DSP Instructions

    Chapter 2. Developing Software for the Cortex-M Family


    Keil Microcontroller Development Kit

    The Tutorial Exercises


    Exercise Building a First Program

    The Blinky Project

    Project Configuration

    Hardware Debug

    Chapter 3. Cortex-M Architecture


    Cortex-M Instruction Set

    Programmer’s Model and CPU Registers

    Program Status Register

    Q Bit and Saturated Math Instructions

    Interrupts and Multicycle Instructions

    Conditional Execution—IF THEN Blocks

    Exercise: Saturated Math and Conditional Execution

    Cortex-M Memory Map and Busses

    Write Buffer

    Memory Barrier Instructions

    System Control Block

    Bit Manipulation

    Exercise: Bit Banding

    Dedicated Bit Manipulation Instructions

    Systick Timer

    Nested Vector Interrupt Controller

    Operating Modes

    Interrupt Handling—Entry

    Interrupt Handling—Exit

    Interrupt Handling—Exit: Important!

    Exercise: Systick Interrupt

    Cortex-M Processor Exceptions

    Priority and Preemption

    Groups and Subgroups

    Run Time Priority Control

    Exception Model

    Exercise: Working with Multiple Interrupts

    Bootloader Support

    Exercise: Bootloader

    Power Management

    Moving from the Cortex-M3




    Chapter 4. Cortex Microcontroller Software Interface Standard


    CMSIS Specifications

    CMSIS Core




    Foundations of CMSIS

    Coding Rules


    CMSIS Core Structure

    Startup Code

    System Code

    Device Header File

    CMSIS Core Header Files

    Interrupts and Exceptions

    Exercise: CMSIS and User Code Comparison

    CMSIS Core Register Access

    CMSIS Core CPU Intrinsic Instructions

    Exercise: Intrinsic Bit Manipulation

    CMSIS SIMD Intrinsics

    CMSIS Core Debug Functions

    Exercise: Simple ITM

    Chapter 5. Advanced Architecture Features


    Cortex Processor Operating Modes

    Exercise: Stack Configuration

    Supervisor Call

    Exercise: SVC

    Pend_SVC Exception

    Example: Pend_SVC

    Interprocessor Events

    Exclusive Access

    Exercise: Exclusive Access

    Memory Protection Unit

    Configuring the MPU

    Exercise: MPU Configuration

    MPU Subregions

    MPU Limitations

    AHB Lite Bus Interface

    Chapter 6. Developing with CMSIS RTOS


    Getting Started

    Setting Up a Project

    First Steps with CMSIS RTOS


    Starting the RTOS

    Exercise: A First CMSIS RTOS Project

    Creating Threads

    Exercise: Creating and Managing Threads

    Thread Management and Priority

    Exercise: Creating and Managing Threads II

    Multiple Instances

    Exercise: Multiple Thread Instances

    Build the Code and Start the Debugger

    Time Management

    Time Delay

    Waiting for an Event

    Exercise: Time Management

    Virtual Timers

    Exercise: Virtual Timer

    Idle Demon

    Exercise Idle Thread

    Interthread Communication

    Exercise: Signals

    Exercise: Interrupt Signal

    Exercise: CMSIS RTX and SVC Exceptions

    Exercise: Semaphore Signaling

    Exercise: Rendezvous

    Exercise: Semaphore Barrier

    Message Queue

    Exercise: Message Queue

    Memory Pool

    Mail Queue

    Exercise: Mailbox

    Chapter 7. Practical DSP for the Cortex-M4


    Cortex-M4 Hardware Floating Point Unit

    FPU Integration

    FPU Registers

    Enabling the FPU

    Exceptions and the FPU

    Using the FPU

    Exercise: Floating Point Unit

    Cortex-M4 DSP and SIMD Instructions

    Exercise: SIMD Instructions

    Exercise: Optimizing DSP Algorithms

    The CMSIS DSP Library

    CMSIS DSP Library Functions

    Exercise: Using the Library

    DSP Data Processing Techniques

    Exercise: FIR Filter with Block Processing

    Fixed Point DSP with Q Numbers

    Exercise: Fixed Point FFT

    Designing for Real-Time Processing

    Buffering Techniques: The Double or Circular Buffer

    Buffering Techniques: FIFO Message Queue

    Balancing the Load

    Exercise: RTX IIR

    Shouldering the Load, the Direct Memory Access Controller

    Chapter 8. Debugging with CoreSight


    CoreSight Hardware

    Debugger Hardware

    CoreSight Debug Architecture

    Exercise: CoreSight Debug

    Hardware Configuration

    Software Configuration

    Debug Limitations

    Instrumentation Trace

    Exercise: Setting Up the ITM

    Software Testing Using the ITM with RTX RTOS

    Error Task

    Software Test Task

    Exercise: Software Testing with the ITM

    Instruction Trace with the ETM

    Exercise: Using the ETM Trace

    System Control Block Debug Support

    Tracking Faults

    Exercise: Processor Fault Exceptions


    Exercise: CMSIS SVD


    Cortex-M0+ MTB

    Exercise: MTB

    Debug Features Summary


    Debug Tools and Software


    Silicon Vendors


    Contact Details


Product details

  • No. of pages: 336
  • Language: English
  • Copyright: © Newnes 2013
  • Published: March 13, 2013
  • Imprint: Newnes
  • eBook ISBN: 9780080982991

About the Author

Trevor Martin

Trevor Martin graduated from Brunel University in 1988 with an Honors degree in Electrical and Electronic Engineering. In the same year he began work as a Junior Hardware engineer at Philips Medical Systems. He joined Hitex in 1992 as a Technical specialist for 8 Bit Microcontroller development tools. This included the 8051,68HC11\05\08 microcontrollers. He also gained experience with networking protocols such as CAN,USB and TCP/IP. Since 2000 he has been supporting ARM based microcontrollers, initially ARM7 and ARM9 CPU then moving to Cortex-M processor. To promote these devices he has worked closely with both NXP and ST and also TI and Freescale to a lesser extent. Since 2005 he has written a number of „Insiders Guide‟ Books which are introductory tutorials to ARM based microcontroller families such as LPC2000, STR9 and STM32. He also runs regular training courses, a general Cortex Microcontroller workshop and also device specific courses.

Affiliations and Expertise

Technical Specialist, Hitex (UK) Ltd., Coventry, England, UK

Ratings and Reviews

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  • Roland Mon Apr 01 2019

    Excellent Introduction to working with Cortex-M!

    The book covers all essential topics on the Cortex-M microcontroller architecture, even the latest addition - the M7. I found the parts on the real-time operating systems very helpful. The practical examples helped to try things out and the understanding.