The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors

Foreword

Preface

Synopsis

About this Book

Contributor Bio-Paul Beckmann

Acknowledgments

Terms and Abbreviations

Conventions

Chapter 1. Introduction to ARM^® Cortex^®-M Processors

Abstract

1.1 What are the ARM^® Cortex^®-M processors?

1.2 Advantages of the Cortex^®-M processors

1.3 Applications of the ARM^® Cortex^®-M processors

1.4 Resources for using ARM^® processors and ARM microcontrollers

1.5 Background and history

Chapter 2. Introduction to Embedded Software Development

Abstract

2.1 What are inside typical ARM^® microcontrollers?

2.2 What you need to start

2.3 Software development flow

2.4 Compiling your applications

2.5 Software flow

2.6 Data types in C programming

2.7 Inputs, outputs, and peripherals accesses

2.8 Microcontroller interfaces

2.9 The Cortex^® microcontroller software interface standard (CMSIS)

Chapter 3. Technical Overview

Abstract

3.1 General information about the Cortex^®-M3 and Cortex-M4 processors

3.2 Features of the Cortex^®-M3 and Cortex-M4 processors

Chapter 4. Architecture

Abstract

4.1 Introduction to the architecture

4.2 Programmer’s model

4.3 Behavior of the application program status register (APSR)

4.4 Memory system

4.5 Exceptions and interrupts

4.6 System control block (SCB)

4.7 Debug

4.8 Reset and reset sequence

Chapter 5. Instruction Set

Abstract

5.1 Background to the instruction set in ARM^® Cortex^®-M processors

5.2 Comparison of the instruction set in ARM^® Cortex^®-M processors

5.3 Understanding the assembly language syntax

5.4 Use of a suffix in instructions

5.5 Unified assembly language (UAL)

5.6 Instruction set

5.7 Cortex^®-M4-specific instructions

5.8 Barrel shifter

5.9 Accessing special instructions and special registers in programming

Chapter 6. Memory System

Abstract

6.1 Overview of memory system features

6.2 Memory map

6.3 Connecting the processor to memory and peripherals

6.4 Memory requirements

6.5 Memory endianness

6.6 Data alignment and unaligned data access support

6.7 Bit-band operations

6.8 Default memory access permissions

6.9 Memory access attributes

6.10 Exclusive accesses

6.11 Memory barriers

6.12 Memory system in a microcontroller

Chapter 7. Exceptions and Interrupts

Abstract

7.1 Overview of exceptions and interrupts

7.2 Exception types

7.3 Overview of interrupt management

7.4 Definitions of priority

7.5 Vector table and vector table relocation

7.6 Interrupt inputs and pending behaviors

7.7 Exception sequence overview

7.8 Details of NVIC registers for interrupt control

7.9 Details of SCB registers for exception and interrupt control

7.10 Details of special registers for exception or interrupt masking

7.11 Example procedures in setting up interrupts

7.12 Software interrupts

7.13 Tips and hints

Chapter 8. Exception Handling in Detail

Abstract

8.1 Introduction

8.2 Exception sequences

8.3 Interrupt latency and exception handling optimization

Chapter 9. Low Power and System Control Features

Abstract

9.1 Low power designs

9.2 Low power features

9.3 Using WFI and WFE instructions in programming

9.4 Developing low power applications

9.5 The SysTick timer

9.6 Self-reset

9.7 CPU ID base register

9.8 Configuration control register

9.9 Auxiliary control register

9.10 Co-processor access control register

Chapter 10. OS Support Features

Abstract

10.1 Overview of OS support features

10.2 Shadowed stack pointer

10.3 SVC exception

10.4 PendSV exception

10.5 Context switching in action

10.6 Exclusive accesses and embedded OS

Chapter 11. Memory Protection Unit (MPU)

Abstract

11.1 Overview of the MPU

11.2 MPU registers

11.3 Setting up the MPU

11.4 Memory barrier and MPU configuration

11.5 Using sub-region disable

11.6 Considerations when using MPU

11.7 Other usages of the MPU

11.8 Comparing with the MPU in the Cortex^®-M0+ processor

Chapter 12. Fault Exceptions and Fault Handling

Abstract

12.1 Overview of fault exceptions

12.2 Causes of faults

12.3 Enabling fault handlers

12.4 Fault status registers and fault address registers

12.5 Analyzing faults

12.6 Faults related to exception handling

12.7 Lockup

12.8 Fault handlers

12.9 Additional information

Chapter 13. Floating Point Operations

Abstract

13.1 About floating point data

13.2 Cortex^®-M4 floating point unit (FPU)

13.3 Lazy stacking in detail

13.4 Using the floating point unit

13.5 Floating point exceptions

13.6 Hints and tips

Chapter 14. Introduction to the Debug and Trace Features

Abstract

14.1 Debug and trace features overview

14.2 Debug architecture

14.3 Debug modes

14.4 Debug events

14.5 Breakpoint feature

14.6 Debug components introduction

14.7 Debug operations

Chapter 15. Getting Started with Keil Microcontroller Development Kit for ARM^®

Abstract

15.1 Overview

15.2 Typical program compilation flow

15.3 Getting started with μVision

15.4 Project options

15.5 Using the IDE and the debugger

15.6 Using the instruction set simulator

15.7 Running programs from SRAM

15.8 Optimization options

15.9 Other hints and tips

Chapter 16. Getting Started with the IAR Embedded Workbench for ARM^®

Abstract

16.1 Overview of the IAR embedded workbench for ARM^®

16.2 Typical program compilation flow

16.3 Creating a simple blinky project

16.4 Project options

16.5 Hints and tips

Chapter 17. Getting Started with the GNU Compiler Collection (gcc)

Abstract

17.1 The GNU Compiler Collection (gcc) toolchain

17.2 Typical development flow

17.3 Creating a simple blinky project

17.4 Overview of the command line options

17.5 Flash programming

17.6 Using Keil™ MDK-ARM with GNU tools for ARM Embedded Processors

17.7 Using CoIDE with GNU tools for ARM^® Embedded Processors

17.8 Commercial gcc-based development suites

Chapter 18. Input and Output Software Examples

Abstract

18.1 Producing outputs

18.2 Re-targeting to the Instrumentation Trace Macrocell (ITM)

18.3 Semi-hosting

18.4 Re-targeting to peripherals

Chapter 19. Using Embedded Operating Systems

Abstract

19.1 Introduction to embedded OSs

19.2 Keil™ RTX Real-Time Kernel

19.3 CMSIS-OS examples

19.4 OS-aware debugging

19.5 Troubleshooting

Chapter 20. Assembly and Mixed Language Projects

Abstract

20.1 Use of assembly code in projects

20.2 Interaction between C and assembly

20.3 Structure of an assembly function

20.4 Examples

20.5 Mixed language projects

20.6 Intrinsic functions

20.7 Idiom recognition

Chapter 21. ARM^® Cortex^®-M4 and DSP Applications

Abstract

21.1 DSP on a microcontroller?

21.2 Dot product example

21.3 Architecture of a traditional DSP processor

21.4 Cortex^®-M4 DSP instructions

21.5 Writing optimized DSP code for the Cortex^®-M4

Chapter 22. Using the ARM^® CMSIS-DSP Library

Abstract

22.1 Overview of the library

22.2 Pre-built binaries

22.3 Function naming convention

22.4 Getting help

22.5 Example 1 – DTMF demodulation

22.6 Example 2 – least squares motion tracking

Chapter 23. Advanced Topics

Abstract

23.1 Decisions and branches

23.2 Performance considerations

23.3 Double-word stack alignment

23.4 Various methods for semaphore implementation

23.5 Non-base Thread enable

23.6 Re-entrant Interrupt Handler

23.7 Bit Data Handling in C

23.8 Startup code

23.9 Stack overflow detection

23.10 Flash patch feature

23.11 Revision versions of the Cortex^®-M3 and Cortex-M4 processors

Chapter 24. Software Porting

Abstract

24.1 Overview

24.2 Porting software from 8-bit/16-bit MCUs to Cortex^®-M MCUs

24.3 Porting software from ARM7TDMI™ to Cortex^®-M3/M4

24.4 Porting software between different Cortex^®-M processors

References

Document

Index

Appendix A. Instruction Set Summary

A.1 Instructions available for both Cortex^®-M3 and Cortex-M4

A.2 Instructions available for Cortex^®-M4

A.3 Floating point instructions for Cortex^®-M4

Appendix B. Graphical Representations of DSP Instructions

Appendix C. Addition of 16-bit Thumb^® Instructions in Recent Architecture Versions

Appendix D. Cortex^®-M3/M4 Exceptions Quick Reference

D.1 Exception types and enable

D.2 Stack frame format

Appendix E. CMSIS-Core Functions Quick Reference

E.1 Exception and interrupt numbers

E.2 NVIC access functions

E.3 System and systick functions

E.4 Core registers access functions

E.5 CMSIS intrinsic functions

E.6 Debug message output function

Appendix F. NVIC and SCB Registers Quick Reference

F.1 NVIC registers

F.2 SCB registers

F.3 Other system control registers not in SCB data structure

F.4 SYSTICK timer registers

F.5 Memory protection unit

F.6 Floating point unit

F.7 SCS Peripheral and Component ID Registers

Appendix G. Cortex^®-M3/M4 Debug Components Programmer’s Model

G.1 Processor core debug registers

G.2 Flash patch and breakpoint unit

G.3 Data watchpoint and trace unit

G.4 Instrumentation trace macrocell

G.5 Trace port interface unit (TPIU)

G.6 AHB-AP (AHB access port)

Appendix H. Connectors for Debug and Trace

H.1 Overview

Appendix I. Troubleshooting Guide

I.1 Overview

I.2 The debugger cannot connect to the development board

I.3 The system does not start

I.4 System not responding

I.5 Fault exceptions

I.6 Understanding the cause of the fault

I.7 Other possible problems