Description

This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design.

Key Features

  • The ability to include reliability calculations and test results in their product design
  • The ability to use reliability data provided to them by their suppliers to make meaningful reliability predictions
  • Have accurate failure rate calculations for calculating warrantee period replacement costs

Readership

Chip designers, electronic system designers and reliability engineers in electronics companies, chip manufacturers and microelectronics/ system designers

Table of Contents

Dedication

Introduction

Chapter 1. Shortcut to Accurate Reliability Prediction

1.1 Background of FIT

1.2 Multiple Failure Mechanism Model

1.3 Acceleration Factor

1.4 New Proportionality Method

1.5 Chip Designer

1.6 System Designer

Chapter 2. M-HTOL Principles

2.1 Constant Rate Assumption

2.2 Reliability Criteria

2.3 The Failure Rate Curve for Electronic Systems

2.4 Reliability Testing

2.5 Accelerated Testing

Chapter 3. Failure Mechanisms

3.1 Time-Dependent Dielectric Breakdown

3.2 Hot Carrier Injection

3.3 Negative Bias Temperature Instability

3.4 Electromigration

3.5 Soft Errors Due to Memory Alpha Particles

Chapter 4. New M-HTOL Approach

4.1 Problematic Zero Failure Criteria

4.2 Single Versus Multiple Competing Mechanisms

4.3 AF Calculation

4.4 Electronic System CFR Approximation/Justification

4.5 PoF-Based Circuits Reliability Prediction Methodology

4.6 Cell Reliability Estimation

4.7 Chip Reliability Prediction

4.8 Matrix Method

Bibliography

Details

No. of pages:
108
Language:
English
Copyright:
© 2014
Published:
Imprint:
Academic Press
eBook ISBN:
9780128008195
Print ISBN:
9780128007471

About the author

Joseph Bernstein

Joseph B. Bernstein is Professor of Electrical Engineering at Ariel University, Ariel, Israel. He received his PhD from MIT, Cambridge, MA, USA, and has previously worked as a Professor at Bar Ilan University, Israel, and at the University of Maryland and the MIT Lincoln Laboratory. He has co-authored two books.

Affiliations and Expertise

Ariel University, Ariel, Israel.

Reviews

This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design.