PowerPC Microprocessor Common Hardware Reference Platform - 1st Edition - ISBN: 9781558603943, 9780128015551

PowerPC Microprocessor Common Hardware Reference Platform

1st Edition

A System Architecture

eBook ISBN: 9780128015551
Imprint: Morgan Kaufmann
Published Date: 29th November 1995
Page Count: 309
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Description

This book defines the architecture requirements and minimum system requirements for a computer system that is designed to become an open industry standard. These requirements provide a description of the devices, interfaces, and data formats required to design and build a PowerPC-based computer. This standard is designed to provide software compatibility for several operating environments. Systems built to these requirements can use industry-standard components currently found in IBM-compatible and Apple® Macintosh® personal computers. These systems are expected to run various future versions of operating systems including Apple Mac OS™, IBM AIX™ and PowerPC™ Editions of IBM OS/2 Warp Connect™, Microsoft Windows NT™ Workstation, Novell Netware™, and SunSoft Solaris™.

This book is the primary source of information for anyone developing a hardware platform, an operating system, or hardware component to be part of these standard systems. It describes the hardware-to-operating-system interface that is essential to anyone building hardware platforms and provides the minimum system configurations that platform designers must meet when building a standard platform. Component manufacturers require this information to produce compatible chips and adapters to use on these platforms, and software developers require the information on mandatory functions and documented interfaces.

The architecture is intended to support a range of PowerPC microprocessor-based system implementations including portable, desktop, and server class systems, and allows multiple operating-system implementations across a wide range of environments and functions. This enables new hardware and software enhancements that are necessary for the development of improved user interfaces, higher performance, and broader operating environments.

Table of Contents

PowerPC™ Microprocessor Common Hardware Reference Platform: A System Architecture
by IBM Inc & Motorola

    Foreword
    List of Figures
    List of Tables
      About this Document
      Goals of the Specification
      Audience for this Document
      Organization of this Document
      Suggested Reading
      Conventions Used in this Document
      Acknowledgments
      Comments on this Document

    Chapter 1 Introduction
      1.1 Platform topology

    Chapter 2 System Requirements
      2.1 System Operation
        2.1.1 Control Flow
        2.1.2 POST
        2.1.3 Boot Phase
        2.1.4 Transfer Phase
        2.1.5 Run-Time
        2.1.6 Termination
      2.2 Firmware
      2.3 Bi-Endian Support
      2.4 64-Bit Addressing Support
      2.5 Minimum System Requirements
        2.5.1 Table Description
      2.6 Options and Extensions

    Chapter 3 System Address Map
      3.1 Address Areas
      3.2 Address Decoding and Translation
        3.2.1 Peripheral I/O Address Translation
        3.2.2 Translation of 32-Bit DMA Addresses in 64-Bit Addressing Systems
      3.3 PC Emulation Option

    Chapter 4 Processor and Memory
      4.1 Processor Architecture
        4.1.1 Processor Architecture Compliance
        4.1.2 PowerPC Microprocessor Differences
        4.1.3 Processor Interface Variations
        4.1.4 PowerPC Architecture Features Deserving Comment
      4.2 Memory Architecture
        4.2.1 System Memory
        4.2.2 Storage Ordering Models
        4.2.3 Memory Controllers
        4.2.4 Cache Memory

    Chapter 5 I/O Bridges
      5.1 PCI Host Bridge (PHB) Architecture
        5.1.1 PHB Implementation Options
        5.1.2 Data Buffering and Instruction Queuing
        5.1.3 Byte Ordering Conventions
        5.1.4 PCI Bus Protocols
        5.1.5 Programming Model
      5.2 I/O Bus to I/O Bus Bridges
        5.2.1 What Must Talk to What
        5.2.2 PCI to PCI Bridges
        5.2.3 PCI to ISA Bridges
        5.2.4 16-Bit PC Card (PCMCIA) and Cardbus PC Card Bridges

    Chapter 6 Interrupt Controller
      6.1 Interrupt Controller Architecture
      6.2 Distributed Implementation - A Proposal

    Chapter 7 Run-Time Abstraction Services
      7.1 RTAS Introduction
      7.2 RTAS Environment
        7.2.1 Machine State
        7.2.2 Register Usage
        7.2.3 RTAS Critical Regions
        7.2.4 Resource Allocation and Use
        7.2.5 Instantiating RTAS
        7.2.6 RTAS Device Tree Properties
        7.2.7 Calling Mechanism and Conventions
        7.2.8 Return Codes
      7.3 RTAS Call Function Definition
        7.3.1 restart-rtas
        7.3.2 NVRAM Access Functions
        7.3.3 Time of Day
        7.3.4 Error and Event Reporting
        7.3.5 PCI Configuration Space
        7.3.6 Operator Interfaces and Platform Control
        7.3.7 Power Management
        7.3.8 Suspend and Hibernate
        7.3.9 Reboot
        7.3.10 Caches
        7.3.11 SMP Support

    Chapter 8 Non-Volatile Memory
      8.1 System Requirements
      8.2 Structure
      8.3 Signatures
      8.4 Architected Partitions
        8.4.1 Open Firmware (0x50)
        8.4.2 Hardware (0x52)
        8.4.3 System (0x70)
        8.4.4 Configuration (0x71)
        8.4.5 Error Log (0x72)
        8.4.6 Multi-Boot (0x73)
        8.4.7 Free Space (0x7F)
      8.5 NVRAM Space Management

    Chapter 9 I/O Devices
      9.1 PCI Devices
        9.1.1 Resource Locking
        9.1.2 PCI Expansion ROMs
        9.1.3 Assignment of Interrupts to PCI Devices
        9.1.4 PCI Devices with Required Register Definitions
        9.1.5 PCI-PCI Bridge Devices
        9.1.6 Graphics Controller and Monitor Requirements for Clients
      9.2 ISA Devices

    Chapter 10 Error and Event Notification
      10.1 Introduction
      10.2 RTAS Error and Event Classes
        10.2.1 Internal Error Indications
        10.2.2 Environmental and Power Warnings
        10.2.3 Power Management Events
      10.3 RTAS Error and Event Information Reporting
        10.3.1 Introduction
        10.3.2 RTAS Error/Event Return Format

    Chapter 11 Power Management
      11.1 Power Management Concepts
        11.1.1 Power Management Policy Versus Mechanism
        11.1.2 Device Power States
        11.1.3 System Power Management States
        11.1.4 System Power Transitory States
        11.1.5 Power Domains and Domain Control Points
        11.1.6 Power Sources
        11.1.7 Batteries
        11.1.8 Power Management Events
        11.1.9 Explicit Transfer of Power Management Policy
        11.1.10 EPA Energy Star Compliance
      11.2 Power-Managed Platform Requirements
        11.2.1 Definition of Power Management Related Parameters Utilized by RTAS
        11.2.2 Open Firmware Device Tree Properties
        11.2.3 General Hardware Requirements
      11.3 Operating System Requirements
        11.3.1 General Requirements

    Chapter 12 The Symmetric Multiprocessor Option
      12.1 SMP System Organization
      12.2 An SMP Boot Process
        12.2.1 SMP-Safe Boot
        12.2.2 Finding the Processor Configuration
        12.2.3 SMP-Efficient Boot
        12.2.4 Use of a Service Processor

    Appendix A Operating System Information
    Appendix B Requirements Summary
    Appendix C Bi-Endian Designs
      C.1 Little-Endian Address and Data Translation
      C.2 Conforming Bi-Endian Designs
        C.2.1 Processor and I/O Mode Control
        C.2.2 Approach#1-Bi-Endian Memory and Bi-Endian I/O Design
        C.2.3 Approach #2-Bi-Endian I/O Design
      C.3 Software Support for Bi-Endian Operation
      C.4 Bi-Model Devices
      C.5 Future Directions in Bi-Endian Architecture

    Appendix D Architecture Migration Notes
    Glossary
    Trademark Information
    Bibliography
    Sources for Documents
    Obtaining Additional Information
    Index

Details

No. of pages:
309
Language:
English
Copyright:
© Morgan Kaufmann 1996
Published:
Imprint:
Morgan Kaufmann
eBook ISBN:
9780128015551