Description

Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors. Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.

Key Features

·Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linköpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington. ·Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.

Readership

Processor designers and system designers in research and industry

Table of Contents

Network Processor Design: Issues and Practics, Volume 2 Contents Preface Chapter 1. Network Processors: Themes and Challenges, Patrick Crowley, Mark Franklin, Haldun Hadimioglu, and Peter Z. Onufryk Part 1. Design Principles Chapter 2. A Programmable Scalable Platform for Next Generation Networking, Christos J.Georgiou, Valentina Salapura, and Monty Denneau Chapter 3. Power Considerations in Network Processor Design, Mark A. Franklin and Tilman Wolf Chapter 4. Worst-Case Execution Time Estimation for Hardware-assisted Multithreaded Processors, Patrick Crowley and Jean-Loup Baer Chapter 5. Multiprocessor Scheduling in Processor-based Router Platforms: Issues and Ideas, Anand Srinivasan, Philip Holman, James Anderson, Sanjoy Baruah and Jasleen Kaur Chapter 6. A Massively Multithreaded Packet Processor, Steve Melvin, Mario Nemirovsky, Enric Musoll, Jeff Huynh, Rodolfo Milito, Hector Urdaneta, and Koroush Saraf Chapter 7. Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, Matthias Gries, Chidamber Kulkarni, Christian Sauer and Kurt Keutzer Chapter 8. Packet Classification and Termination in a Protocol Processor, Ulf Nordqvist and Dake Liu Chapter 9. NP-Click: A Programming Model for the Intel IXP1200, Niraj Shah, William Plishker and Kurt Keutzer Chapter 10. NEPAL: A Framework for Efficiently Structuring Applications for Network Processors, Gokhan Memik and William H. Mangione-Smith Chapter 11. Efficient and Faithful Performance Modeling for Network-Processor Based System Designs, Prashant Pradhan, Wen Xu, Indira Nair and Sambit Sahu Chapter 12. High-speed Legitimacy-based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200, Roshan K. Thomas, Brian Mark, Tommy Johns

Details

No. of pages:
464
Language:
English
Copyright:
© 2004
Published:
Imprint:
Morgan Kaufmann
Print ISBN:
9780121981570
Electronic ISBN:
9780080491943

About the editors

Patrick Crowley

Patrick Crowley is an associate Professor in the Department of Computer Science & Engineering at Washington University in St. Louis, Missouri. His research interests are in computer and network systems architecture, with a current focus on the design of programmable embedded network systems and the invention of superior network monitoring and security techniques. He co-founded the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, and co-edited the three-book series, Network Processor Design. He serves as Associate Editor of the IEEE/ACM Transactions on Networking. In 2007, Crowley was chosen to join the DARPA Computer Science Study Group.

Peter Onufryk

Peter Z. Onufryk received his B.S.E.E. from Rutgers University, M.S.E.E. from Purdue University, and Ph.D. in Electrical and Computer Engineering from Rutgers University. He is currently a director in the Internetworking Products Division at Integrated Device Technology, Inc. where he is responsible for architecture definition and validation of communications products. Before joining IDT, Peter was a researcher for thirteen years at AT&T Labs - Research (formally AT&T Bell Labs) where he worked on communications systems and parallel computer architectures. These included a number of parallel, cache-coherent multiprocessor and dataflow based machines that were targeted towards high performance military systems. Other work there focused on packet telephony and early network processors. Onufryk is a member of the IEEE. He was an organizer and program committee member of the HPCA8 Workshop on Network Processors 2002. Peter was the architect of four communications processors as well as numerous ASICs, boards, and systems.