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Microprocessor Engineering - 1st Edition - ISBN: 9780408013611, 9781483104904

Microprocessor Engineering

1st Edition

Author: B. Holdsworth
eBook ISBN: 9781483104904
Imprint: Butterworth-Heinemann
Published Date: 23rd February 1987
Page Count: 352
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Microprocessor Engineering provides an insight in the structures and operating techniques of a small computer. The book is comprised of 10 chapters that deal with the various aspects of computing. The first two chapters tackle the basic arithmetic and logic processes. The third chapter covers the various memory devices, both ROM and RWM. Next, the book deals with the general architecture of microprocessor. The succeeding three chapters discuss the software aspects of machine operation, while the last remaining three chapters talk about the relationship of the microprocessor with the outside world. The text will be of great use to undergraduate students of various disciplines. Practitioners of computer-related fields with no previous digital experience will find this book useful.

Table of Contents

1 Arithmetic

1.1 Introduction

1.2 Number Systems

1.3 Conversion between Number Systems

1.4 Representation of Numerical Data in a Machine

1.5 Unsigned Arithmetic

1.6 Signed Arithmetic

1.7 Complement Arithmetic

1.8 Addition and Subtraction of 2's Complement Numbers

1.9 Multiplication of 2's Complement Numbers

1.10 Division of 2's Complement Numbers

1.11 Binary Coded Decimal Arithmetic

1.12 10's Complement Arithmetic

1.13 Signed BCD Arithmetic

1.14 Multiplication and Division of BCD Numbers

1.15 Decimal to Binary Conversion

1.16 Fractional Binary Numbers


2 Logic

2.1 Introduction

2.2 Gates

2.3 Inverters

2.4 Alternative Logic Representations

2.5 The Tri-State Gate

2.6 The D-Type Flip-Flop

2.7 The Edge-Triggered D-Type Flip-flop

2.8 The Level-Triggered D-Type Flip-flop

2.9 Asynchronous Controls

2.10 Flip-flop Conversion

2.11 Flip-flop Operating Characteristics

2.12 Registers

2.13 Data Transfer Operations

2.14 The Data Latching Register

2.15 The Tri-State Register

2.16 The Edge-Triggered Register

2.17 Data Selectors or Multiplexers

2.18 Demultiplexers and Decoders

2.19 Encoders

2.20 Parity Generation and Checking

2.21 Comparators

2.22 Arithmetic Circuits

2.23 Arithmetic/Logic Unit


3 Memory

3.1 Introduction

3.2 The Register Representation of Memory

3.3 Memory Timing

3.4 Memory Classification

3.5 ROMs

3.6 PROMs

3.7 EPROMs

3.8 RWMs

3.9 Static MOS RWM

3.10 The Dynamic RWM

3.11 The Bipolar RWM

3.12 Memory Expansion

3.13 Memory Address Decoding

3.14 Absolute Addressing

3.15 Memory Pages


4 Small Computer Architecture

4.1 Introduction

4.2 The Block Diagram of a Microcomputer System

4.3 The Bus System

4.4 Microprocessor Architecture

4.5 Internal Registers

4.6 The Arithmetic/Logic Unit

4.7 Basic Microprocessor Operation

4.8 The 8085A Microprocessor

4.9 The Architecture of the 8085A

4.10 The Operation of the 8085A

4.11 State and Timing Diagrams for the 8085A

4.12 The WAIT State

4.13 The HALT State

4.14 The SDK 85 Expandable Micro-computing Kit

4.15 Other Microprocessors

4.16 The Intel 8080A

4.17 The Zilog Z80

4.18 The Motorola 6800


5 The Instruction Set I: Data Transfer, Arithmetic and Logic Operations

5.1 Introduction

5.2 Machine Code Representation of Instructions

5.3 Mnemonic Representation of Instructions

5.4 Addressing Modes

5.5 Implied Addressing

5.6 Immediate Addressing

5.7 Direct Addressing

5.8 Register and Register Indirect Addressing

5.9 Indexed Addressing

5.10 Relative Addressing

5.11 Modified Page Zero Addressing

5.12 Instruction Groupings for the 8085A

5.13 Data Transfer Instructions

5.14 Transfers Employing Immediate Addressing

5.15 Inter-Register Transfers

5.16 Transfers Using the Direct Addressing Mode

5.17 Transfers Using the Indirect Addressing Mode

5.18 The Input and Output Instructions

5.19 Arithmetic and Logic Operations

5.20 Immediate Arithmetic and Logic Instructions

5.21 Register Arithmetic and Logic Instructions

5.22 Indirect Register Arithmetic and Logic Instructions

5.23 Rotate and Data Shift Instructions

5.24 Miscellaneous Instructions


6 The Instruction Set II: Jump, Call, Return and Stack Control

6.1 Introduction

6.2 Flowcharts

6.3 Basic Flowchart Combinations

6.4 The Jump Instructions

6.5 The Program Implementation of the If-Then/Else Structure

6.6 Program Loops

6.7 A Program Implementation of the SELECT Structure

6.8 Stack Operations and Instructions

6.9 Subroutines

6.10 The Call and Return Instructions


7 Assembly Language Programming and Software Aids

7.1 Introduction

7.2 Source and Object Programs

7.3 The Fields of an Assembly Language Statement

7.4 Manual Assembly

7.5 Assembler Directives

7.6 The Two-Pass Assembler

7.7 Program Execution Time

7.8 Software Generation of Time Delays

7.9 Generation of a Repetitive Waveform Using Software Delays

7.10 Subroutine Linkage

7.11 Re-Entrancy

7.12 Macros

7.13 High Level Languages

7.14 Compilers

7.15 Interpreters

7.16 Monitors and Operating Systems

7.17 Program Libraries


8 Program Controlled Input/Output Data Transfers

8.1 Introduction

8.2 I/O Interfacing

8.3 Isolated and Memory Mapped I/O

8.4 The Input/Output Instructions for the 8085A

8.5 The Timing Diagram for an Isolated I/O Operation in the 8085A

8.6 Design of Peripheral Selection Logic

8.7 Memory Mapped I/O Operations

8.8 Port Selection in a Memory Mapped System

8.9 Assembly Language Instructions for Memory Mapped I/O Devices

8.10 Transfer of Parallel Data under Program Control

8.11 Polling

8.12 Peripheral Interface Chips

8.13 Multi-Function LSI Devices

8.14 Serial Transfer of Data

8.15 Asynchronous Serial Data Transfer

8.16 Synchronous Serial Data Transfer

8.17 Protocol

8.18 The Universal Asynchronous Receiver/Transmitter (UART)

8.19 Communication Techniques with Long Transmission Channels

8.20 The Serial I/O Pins of the 8085A Processor


9 Interrupts

9.1 Introduction

9.2 The Interrupt Process

9.3 Maskable and non-Maskable Interrupts

9.4 The Salient Features of an Interrupt System

9.5 Examination of the Interrupt Line

9.6 Transfer of Control to the Interrupt Service Routine

9.7 Preservation and Restoration of Status

9.8 Identifying the Interrupt Source

9.9 Software Polling

9.10 Vectored Interrupts

9.11 Hardware Polling for Interrupt Identification

9.12 A Priority Interrupt System

9.13 Enabling and Disabling Interrupts

9.14 The 8085A Interrupts

9.15 State Diagram for the 8085A, Including Interrupt Logic

9.16 Interrupt Response of the 8085A

9.17 The 6800 Interrupt Structure

9.18 Direct Memory Access (DMA)

9.19 The HOLD State

9.20 Basic Requirements of a DMA Transfer

9.21 Basic Requirements of a DMA Controller

9.22 DMA with Multiple External Devices

9.23 The Intel 8257 DMA Controller


10 Data Conversion

10.1 Introduction

10.2 Basic Principles of Digital-to-Analogue Conversion

10.3 The Weighted Resistor DAC

10.4 The Use of R/2R Ladder Network in DACs

10.5 Multiplying D/A Converters

10.6 Current Switching DACs

10.7 Converter Coding

10.8 Analogue Polarity

10.9 Resolution

10.10 Errors in D/A Converters

10.11 Settling Time

10.12 Interfacing a DAC to a Source of Digital Data

10.13 The Principles of Analogue-to-Digital Conversion

10.14 Sample and Hold Circuits

10.15 Comparators

10.16 Counting ADCs

10.17 Principle of Successive Approximation Conversion

10.18 Successive Approximation ADC

10.19 Parallel A/D Conversion

10.20 Errors in Analogue-to-Digital Converters

10.21 Software Implementation of ADCs


Appendix Intel 8085A Instruction Set Summary




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© Butterworth-Heinemann 1987
23rd February 1987
eBook ISBN:

About the Author

B. Holdsworth

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