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Microprocessor Architectures and Systems - 1st Edition - ISBN: 9780750600323, 9781483278247

Microprocessor Architectures and Systems

1st Edition


Author: Steve Heath
eBook ISBN: 9781483278247
Imprint: Newnes
Published Date: 14th January 1991
Page Count: 302
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Microprocessor Architectures and Systems: RISC, CISC, and DSP focuses on the developments of Motorola's CISC, RISC, and DSP processors and the advancements of the design, functions, and architecture of microprocessors. The publication first ponders on complex instruction set computers and 32-bit CISC processors. Discussions focus on MC68881 and MC68882 floating point coprocessors, debugging support, MC68020 32-bit performance standard, bus interfaces, MC68010 SUPERVISOR resource, and high-level language support. The manuscript then covers the RISC challenge, digital signal processing, and memory management and caches. Topics include implementing memory systems, multitasking and user/supervisor conflicts, partitioning the system, cache size and organization, DSP56000 family, MC88100 programming model, M88000 family, and the 80/20 rule. The text examines the selection of a microprocessor architecture, changing design cycle, semiconductor technology, multiprocessing, and real-time software, interrupts, and exceptions. Concerns include locating associated tasks, MC88100 interrupt service routines, single- and multiple-threaded operating systems, and the MC68300 family. The publication is a valuable reference for computer engineers and researchers interested in microprocessor architectures and systems.

Table of Contents



1 Complex Instruction Set Computers

8-Bit Microprocessors: The Precursors of CISC

8-Bit Microprocessor Register Models


Addressing Memory

System Integrity

Requirements for a New Processor Architecture

Software Compatibility

Enter the MC68000

Complex Instructions, Microcode and Nanocod

The MC68000 Hardware

M68000 Asynchronous Bus

M6800 Synchronous Bus


Error Recovery and Control Signals

Bus Arbitration

Typical System

The Register Set


Exceptions and the Vector Table

Addressing Modes

Instruction Set

Multitasking Operating Systems

High-Level Language Support

The MC68010 Virtual Memory Processor

MC68010 SUPERVISOR Resource

Other Improvements

The MC68008

The Story Continues

2 32-Bit CISC Processors

Enter HCMOS Technology

Architectural Challenges

The MC68020 32-Bit Performance Standard

The Programmer's Model

Bus Interfaces

Dynamic Bus Sizing

On-Chip Instruction Cache

Debugging Support

Coprocessor Interface

MC68881 and MC68882 Floating Point Coprocessors

The MC68851 Paged Memory Management Unit (PMMU)

The MC68030, the First Commercial 50 MHz Processor

3 The RISC Challenge

The 80/20 Rule

The Initial RISC Research

The M88000 Family

The MC88100 Programming Model

The MC88100 Instruction Set

MC88100 External Functions

MC88200 Cache MMU

The MBUS Protocol

4 Digital Signal Processing

Processor Requirements

The DSP56000 Family

The Programming Model

5 Memory, Memory Management and Caches

Achieving Processor Throughput

Partitioning the System

Shadow RAM


Memory Management

Multitasking and User/Supervisor Conflicts

Cache Size and Organization

Cache Coherency

Implementing Memory Systems


6 Real-Time Software, Interrupts and Exceptions

What is Real-Time Software?

Responding to an Interrupt

Interrupting the Processor

Servicing the Interrupt

Locating Associated Tasks

Context Switches

Improving Performance

Interrupting an MC88100

MC88100 Interrupt Service Routines

Improving Software Performance

Interrupting the DSP56000

The M68300 Family


7 Multiprocessing

SISD - Single Instruction, Single Data

SIMD — Single Instruction, Multiple Data

MIMD - Multiple Instruction, Multiple Data

MISD — Multiple Instruction, Single Data

Constructing a MIMD Architecture

Fault-Tolerant Systems

Single- and Multiple-Threaded Operating Systems

8 Application Ideas

1 MC68020 and MC68030 Design Technique for High-Reliability Applications

2 Upgrading 8-Bit Systems

3 Transparent Update Techniques for Digit Filters Using the DSP56000

4 Motor and Servo Control

9 Semiconductor Technology

Silicon Technology

CMOS and Bipolar Technology

Fabrication Technology


Processor Technology

Memory Technology

Science Fiction or Not?

10 The Changing Design Cycle

The Shortening Design Cycle

The Double-Edged Sword of Technology

Make v. Buy

Simulation v. Emulation

11 The Next Generations

Enter the MC68040

The MC68300 Family

Improving the Instruction Set

DSP96000 - Combining Integration and Performance

12 Selecting a Microprocessor Architecture

Meeting Performance Needs

Software Support

Development Support


Built-in Obsolescence

Market Changes

Considering All the Options


A Benchmarking

B Binary Compatibility Standards



No. of pages:
© Newnes 1991
14th January 1991
eBook ISBN:

About the Author

Steve Heath

Senior Staff Engineer, European Strategy and Technology Development, Motorola Semiconductors, Steve Heath has written 15 books on topics covering Apple and IBM PCs, processor architectures, UNIX and Windows NT operating systems.

Affiliations and Expertise

Motorola Semiconductors, Newton, U.K.

Ratings and Reviews