Chapter 1: FPGA Overview: Architecture and CAD
1.2 FPGA Logic Resources Architecture
1.3 FPGA Routing Resources Architecture
1.4 CAD for FPGAs
1.5 Versatile Place and Route (VPR) CAD Tool
Chapter 2: Power Dissipation in Modern FPGAs
2.1 CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits
2.2 Dynamic Power in FPGAs
2.3 Leakage Power in FPGAs
Chapter 3: Power Estimation in FPGAs
3.2 Power Estimation in VLSI: An Overview
3.3 Commercial FPGA Power Estimation Techniques
3.4 A Survey of FPGA Power Estimation Techniques
3.5 A Complete Analytical FPGA Power Model under Spatial Correlation
Chapter 4: Dynamic Power Reduction Techniques in FPGAs
4.1 Multiple Supply Voltages
4.2 Reducing Glitches in FPGAs
4.3 CAD Techniques for Reducing Dynamic Power in FPGAs
Chapter 5: Leakage Power Reduction in FPGAs Using MTCMOS Techniques
5.2 MTCMOS FPGA Architecture
5.3 Sleep Transistor Design and Discharge Current Processing
5.4 Activity Profile Generation
5.5 Activity Packing Algorithms
5.6 Power Estimation
5.7 Results an Discussion
Chapter 6: Leakage Power Reduction in FPGAs Through Input Pin Reordering
6.1 Leakage Power and Input State Dependency in FPGAs
6.2 Proposed Input Pin Reordering Algorithm
6.3 Experimental Results
Low-Power Design of Nanometer FPGAs Architecture and EDA is an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign.
- Low-power techniques presented at key FPGA design levels for circuits, architectures, and electronic design automation, form critical, "bridge" guidelines for codesign
- Comprehensive review of leakage-tolerant techniques empowers designers to minimize power dissipation
- Provides valuable tools for estimating power efficiency/savings of current, low-power FPGA design techniques
Researchers, Circuit-Design Professionals, and EE/ECE Graduate Students concerned with low-power FPGA design. This includes designers at companies globally such as Xilinx, Altera, Actel, Cypress, Lattice Semiconductor, TI, Mentor Graphics, Cadence, Synopsis, Magma, Quicklogic, National Semiconductor, and Freescale.
- No. of pages:
- © Morgan Kaufmann 2009
- 28th September 2009
- Morgan Kaufmann
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Hassan Hassan is currently a staff engineer in the timing and power group at Actel Corporation. He has authored/coauthored more than 20 papers in international journals and conferences. His research interests include integrated circuit design and design automation for deep submicron VLSI systems. He is also a member of the program committee for several IEEE conferences. Dr. Hassan received his Ph.D. in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2008.
Staff Engineer in the timing and power group at Actel Corporation.
Mohab Anis is a tenured Associate Professor at the Department of Electrical and Computer Engineering, University of Waterloo. During 2009, he was with the Electronics Engineering Department at the American University in Cairo. Dr. Anis received his Ph.D. in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2003. Dr. Anis is an Associate Editor of the IEEE Transactions on Circuits and Systems - II, Microelectronics Journal, Journal of Circuits, Systems and Computers, ASP Journal of Low Power Electronics, and VLSI Design. He was awarded the 2009 Early Research Award, the 2004 Douglas R. Colton Medal for Research Excellence in recognition of excellence in research leading to new understanding and novel developments in Microsystems in Canada and the 2002 International Low-Power Design Contest.
Tenured Associate Professor at the Department of Electrical and Computer Engineering, University of Waterloo.