Low-Power Design of Nanometer FPGAs

Chapter 1: FPGA Overview: Architecture and CAD
   1.1 Introduction
   1.2 FPGA Logic Resources Architecture
   1.3 FPGA Routing Resources Architecture
   1.4 CAD for FPGAs
   1.5 Versatile Place and Route (VPR) CAD Tool
Chapter 2: Power Dissipation in Modern FPGAs
   2.1 CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits
   2.2 Dynamic Power in FPGAs
   2.3 Leakage Power in FPGAs
Chapter 3: Power Estimation in FPGAs
   3.1 Introduction
   3.2 Power Estimation in VLSI: An Overview
   3.3 Commercial FPGA Power Estimation Techniques
   3.4 A Survey of FPGA Power Estimation Techniques
   3.5 A Complete Analytical FPGA Power Model under Spatial Correlation
Chapter 4: Dynamic Power Reduction Techniques in FPGAs
   4.1 Multiple Supply Voltages
   4.2 Reducing Glitches in FPGAs
   4.3 CAD Techniques for Reducing Dynamic Power in FPGAs
Chapter 5: Leakage Power Reduction in FPGAs Using MTCMOS Techniques
   5.1 Introduction
   5.2 MTCMOS FPGA Architecture
   5.3 Sleep Transistor Design and Discharge Current Processing
   5.4 Activity Profile Generation
   5.5 Activity Packing Algorithms
   5.6 Power Estimation
   5.7 Results an Discussion
Chapter 6: Leakage Power Reduction in FPGAs Through Input Pin Reordering
   6.1 Leakage Power and Input State Dependency in FPGAs
   6.2 Proposed Input Pin Reordering Algorithm
   6.3 Experimental Results
   6.4 Conclusion