Logical Effort

Logical Effort

Designing Fast CMOS Circuits

1st Edition - February 2, 1999

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  • Authors: Ivan Sutherland, Robert Sproull, David Harris
  • Paperback ISBN: 9781558605572

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Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.

Key Features

  • Explains the method and how to apply it in two practically focused chapters.
  • Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
  • Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
  • Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
  • Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
  • Presents a complete derivation of the method-so you see how and why it works.


This book is intended for anyone who designs CMOS integrated circuits.

Table of Contents

  • Contents

    1 The Method of Logical Effort

    1.1 Introduction

    1.2 Delay in a logic gate

    1.3 Multi­stage logic networks

    1.4 Choosing the best number of stages

    1.5 Summary

    1.6 Exercises

    2 Design Examples

    2.1 The AND function of eight inputs

    2.1.1 Calculating gate sizes

    2.2 Decoder

    2.2.1 Generating complementary inputs

    2.3 Synchronous arbitration

    2.3.1 The original circuit

    2.3.2 Improving the design

    2.3.3 Restructuring the problem

    2.4 Summary

    2.5 Exercises

    3 Deriving the Method of Logical Effort

    3.1 Model of a logic gate

    3.2 Delay in a logic gate

    3.3 Minimizing delay along a path

    3.4 Choosing the length of a path

    3.5 Using the wrong number of stages

    3.6 Using the wrong gate size

    3.7 Summary

    3.8 Exercises

    4 Calculating the Logical Effort of Gates

    4.1 Definitions of logical effort

    4.2 Grouping input signals

    4.3 Calculating logical effort

    4.4 Asymmetric logic gates

    4.5 Catalog of logic gates

    4.5.1 NAND gate

    4.5.2 NOR gate

    4.5.3 Multiplexers, tri­state inverters

    4.5.4 XOR, XNOR, and parity gates

    4.5.5 Majority gate

    4.5.6 Adder carry chain

    4.5.7 Dynamic latch

    4.5.8 Dynamic Muller C­element

    4.5.9 Upper bounds on logical effort

    4.6 Estimating parasitic delay

    4.7 Properties of logical effort

    4.8 Exercises

    5 Calibrating the Model

    5.1 Calibration technique

    5.2 Designing test circuits

    5.2.1 Rising, falling, and average delays

    5.2.2 Choice of input

    5.2.3 Parasitic capacitance

    5.2.4 Process sensitivity

    5.3 Other characterization methods

    5.3.1 Data sheets

    5.3.2 Test chips

    5.4 Calibrating special circuit families

    5.5 Summary

    5.6 Exercises

    6 Asymmetric Logic Gates

    6.1 Designing asymmetric logic gates

    6.2 Applications of asymmetric logic gates

    6.2.1 Multiplexers

    6.3 Summary

    6.4 Exercises

    7 Unequal Rising and Falling Delays

    7.1 Analyzing delays

    7.2 Case analysis

    7.2.1 Skewed gates

    7.2.2 Impact of fl and ¯ on logical effort

    7.3 Optimizing CMOS P=N ratios

    7.4 Summary

    7.5 Exercises

    8 Circuit Families

    8.1 Pseudo­NMOS circuits

    8.1.1 Symmetric NOR gates

    8.2 Domino circuits

    8.2.1 Logical effort of dynamic gates

    8.2.2 Stage effort of domino circuits

    8.2.3 Building logic in static gates

    8.2.4 Designing dynamic gates

    8.3 Transmission gates

    8.4 Summary

    8.5 Exercises

    9 Forks of Amplifiers

    9.1 The fork circuit form

    9.2 How many stages should a fork use?

    9.3 Summary

    9.4 Exercises

    10 Branches and Interconnect

    10.1 Circuits that branch at a single input

    10.1.1 Branch paths with equal lengths

    10.1.2 Branch paths with unequal lengths

    10.2 Branches after logic

    10.3 Circuits that branch and recombine

    10.4 Interconnect

    10.4.1 Short wires

    10.4.2 Long wires

    10.4.3 Medium wires

    10.5 A design approach

    10.6 Exercises

    11 Wide Structures

    11.1 An n­input AND structure

    11.1.1 Minimum logical effort

    11.1.2 Minimum delay

    11.1.3 Other wide functions

    11.2 An n­input Muller C­element

    11.2.1 Minimum logical effort

    11.2.2 Minimum delay

    11.3 Decoders

    11.3.1 Simple decoder

    11.3.2 Predecoding

    11.3.3 Lyon­Schediwy decoder

    11.4 Multiplexers

    11.4.1 How wide should a multiplexer be?

    11.4.2 Medium­width multiplexers

    11.5 Summary

    11.6 Exercises

    12 Conclusions

    12.1 The theory of logical effort

    12.2 Insights from logical effort

    12.3 A design procedure

    12.4 Other approaches to path design

    12.4.1 Simulate and tweak

    12.4.2 Equal fanout

    12.4.3 Equal delay

    12.4.4 Numerical optimization

    12.5 Shortcomings of logical effort

    12.6 Parting words

    A Cast of Characters

    B Reference process parameters

    C Logical Effort Tools

    C.1 Library characterization

    C.2 Wide gate design

    D Solutions

    D.1 Chapter 1

    D.2 Chapter 2

    D.3 Chapter 3

    D.4 Chapter 4

    D.5 Chapter 5

    D.6 Chapter 6

    D.7 Chapter 7

    D.8 Chapter 8

    D.9 Chapter 9

    D.10 Chapter 10

    D.11 Chapter 11

Product details

  • No. of pages: 256
  • Language: English
  • Copyright: © Morgan Kaufmann 1999
  • Published: February 2, 1999
  • Imprint: Morgan Kaufmann
  • Paperback ISBN: 9781558605572

About the Authors

Ivan Sutherland

Ivan E. Sutherland, a vice president and fellow at Sun Microsystems, received the Turing Award and the Von Neumann Medal for his pioneering contributions in the fields of computer graphics and microelectronic design.

Robert Sproull

Robert F. Sproull is an internationally noted expert on the design of graphics hardware and software. He too is a vice president and fellow at Sun.

David Harris

David Harris
David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.

Affiliations and Expertise

Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA

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