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- Fully Depleted Silicon on Oxide Transistor and Compact Model
2. Core Model for Independent Multigate MOSFETs
3. Channel Current Model With Real Device Effects in BSIM-IMG
4. Leakage Current and Thermal Effects
5. Model for Terminal Charges and Capacitances in BSIM-IMG
6. Parameter Extraction With BSIM-IMG Compact Model
7. Testing BSIM-IMG Model Quality
8. High-Frequency and Noise Models in BSIM-IMG
Industry Standard FDSOI Compact Model BSIM-IMG for IC Design helps readers develop an understanding of a FDSOI device and its simulation model. It covers the physics and operation of the FDSOI device, explaining not only how FDSOI enables further scaling, but also how it offers unique possibilities in circuits. Following chapters cover the industry standard compact model BSIM-IMG for FDSOI devices. The book addresses core surface-potential calculations and the plethora of real devices and potential effects. Written by the original developers of the industrial standard model, this book is an excellent reference for the new BSIM-IMG compact model for emerging FDSOI technology.
The authors include chapters on step-by-step parameters extraction procedure for BSIM-IMG model and rigorous industry grade tests that the BSIM-IMG model has undergone. There is also a chapter on analog and RF circuit design in FDSOI technology using the BSIM-IMG model.
- Provides a detailed discussion of the BSIM-IMG model and the industry standard simulation model for FDSOI, all presented by the developers of the model
- Explains the complex operation of the FDSOI device and its use of two independent control inputs
- Addresses the parameter extraction challenges for those using this model
Semiconductor engineers, Materials Scientists, Circuit Designers, Researchers in electronic devices and circuits
- No. of pages:
- © Woodhead Publishing 2019
- 21st May 2019
- Woodhead Publishing
- Paperback ISBN:
- eBook ISBN:
Chenming Hu is Distinguished Chair Professor Emeritus at UC Berkeley. He was the Chief Technology Officer of TSMC and founder of Celestry Design Technologies. He is best known for developing the revolutionary 3D transistor FinFET that powers semiconductor chips beyond 20nm. He also led the development of BSIM-- the industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. His honors include the Asian American Engineer of the Year Award, IEEE Andrew Grove Award and Solid Circuits Award as well as Nishizawa Medal, and UC Berkeley's highest honor for teaching-- the Berkeley Distinguished Teaching Award.
Professor Emeritus, University of California, Berkeley, CA, USA
Sourabh Khandelwal is currently a Postdoctoral Researcher in the BSIM Group, University of California, Berkeley. Sourabh received his PhD degree from Norwegian University of Science and Technology in 2013 and Masters’ degree from Indian Institute of Technology (IIT) Bombay in 2007. From 2007 – 2010 he worked as a Research Engineer at IBM Semiconductor Research and Development Centre, developing compact models for RF SOI devices. He holds a patent and has authored several research papers in the area of device modeling and characterization. His PhD work on GaN compact model is under consideration for industry standardization by the Compact Model Coalition.
Research Faculty, Dept. of Electrical Engineering, University of South Florida, Tampa, USA
Yogesh Singh Chauhan is a professor at Indian Institute of Technology Kanpur, India. He was with Semiconductor Research & Development Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of several industry standard SPICE models: ASM-GaN-HEMT model, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research interests are characterization, modeling, and simulation of semiconductor devices and RF circuit design. He is the Fellow of IEEE, Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He has served in the technical program committees of IEDM, SISPAD, ESSDERC, EDTM, and VLSI Design conferences. He has published more than 250 papers in international journals and conferences.
Associate Professor at the Dept. of Electrical Engineering, Indian Institute of Technology Kanpur
Director of RF Innovation at Globalfoundries, USA
Director of RF Innovation, Globalfoundaries, USA
Principal Member of Technical Staff at Globalfoundries USA
Principal Member of Technical Staff, Globalfoundries, USA
Juan Pablo Duarte Sepúlveda is currently working toward his PhD. degree at the University of California, Berkeley. He received his BS (2010) and MS (2012) degrees in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST). He held a position as a lecturer at Universidad Tecnica Federico Santa Maria, Valparaiso, Chile, in 2012. He has authored many papers in nanoscale semiconductor device modeling and characterization. He received the Best Student Paper Award at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) for the paper “Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs”.
University of California, Berkeley, USA
Pragya Kushwaha is currently a Postdoctoral Researcher with Prof. Chenming Hu in the BSIM Device Modeling Group at University of California, Berkeley. She received her PhD degree from Indian Institute of Technology Kanpur, India in 2017. She has authored several national and international research papers in the area of semiconductor device modeling and characterization. During her PhD, she has developed a complete RF compact model for FDSOI transistors under the frame work of industry standard BSIM-IMG compact model. Her current research interests include modeling, simulation, and characterization of advanced semiconductor devices such as nanowires, NCFETs, PD/FDSOIs, FinFETs, tunnel FETs, high-voltage FETs, and bulk MOSFETs.
Postdoctoral Researcher, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA
Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization.
Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA
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