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High Speed Digital Design discusses the major factors to consider in designing a high speed digital system and how design concepts affect the functionality of the system as a whole. It will help you understand why signals act so differently on a high speed digital system, identify the various problems that may occur in the design, and research solutions to minimize their impact and address their root causes. The authors offer a strong foundation that will help you get high speed digital system designs right the first time.
Taking a systems design approach, High Speed Digital Design offers a progression from fundamental to advanced concepts, starting with transmission line theory, covering core concepts as well as recent developments. It then covers the challenges of signal and power integrity, offers guidelines for channel modeling, and optimizing link circuits. Tying together concepts presented throughout the book, the authors present Intel processors and chipsets as real-world design examples.
- Provides knowledge and guidance in the design of high speed digital circuits
- Explores the latest developments in system design
- Covers everything that encompasses a successful printed circuit board (PCB) product
- Offers insight from Intel insiders about real-world high speed digital design
Computer engineers, system designers, and students in these disciplines seeking knowledge and guidance in the design of high speed signaling and interconnects.
- About the Authors/Contributors
- About the Authors
- About the Contributors
- Chapter 1. Transmission line fundamentals
- Basic Electromagnetics
- Transmission Line Theory
- Transmission Line Structures
- Chapter 2. PCB design for signal integrity
- Differential Signaling
- Time Domain Analysis
- Frequency Domain Analysis
- Stack-Up Design
- PCB Layout Optimization
- Chapter 3. Channel modeling and simulation
- Transmission Lines
- 3D Modeling
- Plated-Through-Hole Via
- Chapter 4. Link circuits and architecture
- Types of Link Circuit Architectures
- Clock and Data Recovery
- Forwarded Clock Receiver
- Design for Test/Manufacture
- Chapter 5. Measurement and data acquisition techniques
- Digital Oscilloscope Measurement
- TDR Measurements
- Vector Network Analyzer Measurement
- Chapter 6. Designing and validating with Intel processors
- Designing Systems with Intel Devices
- System Validation with Intel Devices
- No. of pages:
- © Morgan Kaufmann 2015
- 17th August 2015
- Morgan Kaufmann
- Paperback ISBN:
- eBook ISBN:
Hanqiao Zhang is an Analog Engineer at Intel and holds a PhD degree in Electromagnetics and Microwave Engineering from Clemson University. Hanqiao joined Intel Xeon product electrical validation team in 2011, where he worked on generations of Intel high-speed digital systems. He developed methodologies for validating high-speed interfaces, such as PCI Express and Quick Path Interface (QPI). Hanqiao is now a signal integrity engineer with Intel Data Center Group. He is involved in mission-critical high-performance servers signal integrity design, bring up, validation and debug.
Intel, DuPont, WA, USA
Steve Krooswyk has been at Intel since 2003 when we joined as a signal integrity engineer for EPSD server development. In 2009, Steve transitioned into the signal integrity lead for PCI Express in Intel’s Enterprise Platform Technology Division (EPTD). In addition to server products, his experience includes involvement in the PCI Express 3.0 and 4.0 specifications. He holds a B.S. and M.S. in electrical engineering from the University of South Carolina.
signal integrity lead for PCI Express in Intel’s Enterprise Platform Technology Division (EPTD), Intel, Columbia, SC, USA
Jeffrey Ou joined Intel in 1999 as an analog design engineer in CMOS RF transceiver design. In 2006, Jeffrey transitioned to Xeon processor product design team in Server Development Group (SDG) developing a serial I/O module configurable for PCI Express and Quick Path Interface (QPI). Since then Jeffrey has been involved in several generations of Xeon products from design to post silicon validation. In 2012, Jeffrey was recognized as a tech lead in SDG, and continued to develop the cutting-edge high speed serial I/O modules for server products. Jeffrey holds a PhD degree in EECS from UC Berkeley and is a member of IEEE.
Jeffrey Ou, Tech Lead in Server Development Group, Intel
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