Secure CheckoutPersonal information is secured with SSL technology.
Free ShippingFree global shipping
No minimum order.
Chapter 1 Alternative FPGA Architectures 1.1 A word of warning 1.2 A little background information 1.3 Antifuse versus SRAM versus … 1.4 Fine-, medium-, and coarse-grained architectures 1.5 MUX- versus LUT-based logic blocks 1.6 CLBs versus LABs versus slices 1.7 Fast carry chains 1.8 Embedded RAMs 1.9 Embedded multipliers, adders, MACs, etc. 1.10 Embedded processor cores (hard and soft) 1.11 Clock trees and clock managers 1.12 General-purpose I/O 1.13 Gigabit transceivers 1.14 Hard IP, soft IP, and firm IP 1.15 System gates versus real gates 1.16 FPGA years
Chapter 2 Design Techniques, Rules, and Guidelines 2.1 Hardware Description Languages 2.2 Top-Down Design 2.3 Synchronous Design 2.4 Floating Nodes 2.5 Bus Contention 2.6 One-Hot State Encoding 2.7 Design For Test (DFT) 2.8 Testing Redundant Logic 2.9 Initializing State Machines 2.10 Observable Nodes 2.11 Scan Techniques 2.12 Built-In Self-Test (BIST) 2.13 Signature Analysis 2.14 Summary
Chapter 3 A VHDL Primer: The Essentials 3.1 Introduction 3.2 Entity: model interface 3.3 Architecture: model behavior 3.4 Process: basic functional unit in VHDL 3.5 Basic variable types and operators 3.6 Decisions and loops 3.7 Hierarchical design 3.8 Debugging models 3.9 Basic data types 3.10 Summary
Chapter 4 Modeling Memories 4.1 Memory Arrays 4.2 Modeling Memory Functionality 4.3 VITAL_Memory Path Delays 4.4 VITAL_Memory Timing Constraints 4.5 Preloading Memories 4.6 Modeling Other Memory Types 4.7 Summary
Chapter 5 Introduction to Synchronous State Machine Design and Analysis 5.1 Introduction 5.2 Models For Sequential Machines 5.3 The Fully Documented State Diagram 5.4 The Basic Memory Cells 5.5 Introduction To Flip-Flops 5.6 Procdure For FSM (Flip-Flop) Design And The Mapping Algorithm 5.7 The D Flip-Flops: General 5.8 Flip-Flop Conversion: The T, JK Flip-Flops And Miscellaneous Flip-Flops 5.9 Latches And Flip-Flops With Serious Timing Problems: A Warning 5.10 Asynchronous Preset And Clear Overrides 5.11 Setup And Hold-Time Requirements Of Flip-Flops 5.12 Design Of Simple Synchronous State Machines With Edge-Triggered Flip-Flops: Map Conversion 5.13 Analysis Of Simple State Machines 5.14 VHDL Description Of Simple State Machines 5.15 Further Reading
Chapter 6 Embedded Processors 6.1 Introduction 6.2 A simple embedded processor 6.3 Soft core processors on an FPGA 6.4 Summary
Chapter 7 Digital Signal Processing 7.1 Overview 7.2 Basic DSP System 7.3 Essential DSP terms 7.4 DSP architectures 7.5 parallel execution in DSP Components 7.6 parallel execution in FPGA 7.7 When to Use FPGAs for DSP 7.8 FPGA DSP Design Considerations 7.9 FIR Filter Concept Example 7.10 Summary
Chapter 8 Basics of Embedded Audio Processing 8.1 Introduction 8.2 Audio Sources and Sinks 8.3 Interconnections 8.4 Dynamic Range and Precision 8.5 Audio Processing Methods 8.6 What’s Next?
Chapter 9 Basics of Embedded Video and Image Processing 9.1 Introduction 9.2 Broadcast TV—NTSC and PAL 9.3 Color Spaces 9.4 Digital Video 9.5 A Systems View of Video 9.6 Embedded Video processing Considerations 9.7 Compression/Decompression 9.8 What’s Next?
Chapter 10 Programming Streaming FPGA Applications Using Block Diagrams In Simulink 10.1 Designing High-Performance Datapaths Using Stream-Based Operators 10.2 An Image-Processing Design Driver 10.3 Specifying Control In Simulink 10.4 Component Reuse: Libraries Of Simple And Complex Subsystems 10.5 Summary 10.6 References
Chapter 11 Ladder and functional block programming 11.1 Ladder diagrams 11.2 Logic functions 11.3 Latching 11.4 Multiple outputs 11.5 Entering programs 11.6 Function blocks 11.7 Program examples 11.8 Problems
Chapter 12 Timers 12.1 Types of timers 12.2 Programming timers 12.3 Off-delay timers 12.4 Pulse timers 12.5 Programming examples 12.6 Problems
All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Clive "Max" Maxfield renowned author, columnist, and editor of PL DesignLine has selected the very best FPGA design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of FPGA design from design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving FPGA design problems and how to successfully apply theory to actual design tasks. The material has been selected for its timelessness as well as for its relevance to contemporary FPGA design issues.
Contents Chapter 1 Alternative FPGA Architectures Chapter 2 Design Techniques, Rules, and Guidelines Chapter 3 A VHDL Primer: The Essentials Chapter 4 Modeling Memories Chapter 5 Introduction to Synchronous State Machine Design and Analysis Chapter 6 Embedded Processors Chapter 7 Digital Signal Processing Chapter 8 Basics of Embedded Audio Processing Chapter 9 Basics of Embedded Video and Image Processing Chapter 10 Programming Streaming FPGA Applications Using Block Diagrams In Simulink Chapter 11 Ladder and functional block programming Chapter 12 Timers
Hand-picked content selected by Clive "Max" Maxfield, character, luminary, columnist, and author Proven best design practices for FPGA development, verification, and low-power *Case histories and design examples get you off and running on your current project
Electronics Designers and Programmers; Application Engineers; Hardware Engineers; Software Engineers
- No. of pages:
- © Newnes 2009
- 18th February 2009
- Paperback ISBN:
- eBook ISBN:
Clive "Max" Maxfield received a BS in Control Engineering from Sheffield Polytechnic, England in 1980. He began his career as a mainframe CPU designer for International Computers Limited (ICL) in Manchester, England. Max now finds himself a member of the technical staff (MTS) at Intergraph Electronics, Huntsville, Alabama. Max is the author of dozens of articles and papers appearing in magazines and at technical conferences around the world. Max's main area of interest are currently focused in the analog, digital, and mixed-signal simulation of integrated circuits and multichip modules.
Engineer, TechBytes, and Editor of PLDesignline.com EDA industry consultant, EDN columnist, and Embedded Systems Guru
Elsevier.com visitor survey
We are always looking for ways to improve customer experience on Elsevier.com.
We would like to ask you for a moment of your time to fill in a short questionnaire, at the end of your visit.
If you decide to participate, a new browser tab will open so you can complete the survey after you have completed your visit to this website.
Thanks in advance for your time.