Design Recipes for FPGAs: Using Verilog and VHDL
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Design Recipes for FPGAs: Using Verilog and VHDL provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, the book gives ‘easy-to-find’ design techniques and templates at all levels, together with functional code. Written in an informal and ‘easy-to-grasp’ style, it goes beyond the principles of FPGA s and hardware description languages to actually demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. This book's ‘easy-to-find’ structure begins with a design application to demonstrate the key building blocks of FPGA design and how to connect them, enabling the experienced FPGA designer to quickly select the right design for their application, while providing the less experienced a ‘road map’ to solving their specific design problem. The book also provides advanced techniques to create ‘real world’ designs that fit the device required and which are fast and reliable to implement. This text will appeal to FPGA designers of all levels of experience. It is also an ideal resource for embedded system development engineers, hardware and software engineers, and undergraduates and postgraduates studying an embedded system which focuses on FPGA design.
Key Features
- A rich toolbox of practical FGPA design techniques at an engineer's finger tips
- Easy-to-find structure that allows the engineer to quickly locate the information to solve their FGPA design problem, and obtain the level of detail and understanding needed
Readership
Embedded system development engineers, FPGA engineers, hardware and software engineers. Undergraduates and postgraduates studying an embedded system which focuses on FPGA design.
Table of Contents
- ACKNOWLEDGEMENTS
PREFACE
TABLE OF CONTENTS
TABLE OF FIGURES
SECTION 1: INTRODUCTION
CHAPTER 1: INTRODUCTION
1.1 OVERVIEW
1.2 WHY FPGAS?
CHAPTER 2: AN FPGA PRIMER
2.1 INTRODUCTION
2.2 FPGA EVOLUTION
2.3 PROGRAMMABLE LOGIC DEVICES
2.4 FIELD PROGRAMMABLE GATE ARRAYS
2.5 FPGA DESIGN TECHNIQUES
2.6 DESIGN CONSTRAINTS USING FPGAS
2.7 SUMMARY
CHAPTER 3: A VHDL PRIMER – THE ESSENTIALS
3.1 INTRODUCTION
3.2 ENTITY – MODEL INTERFACE
3.3 ARCHITECTURE – MODEL BEHAVIOUR
3.4 PROCESS – BASIC FUNCTIONAL UNIT IN VHDL
3.5 BASIC VARIABLE TYPES AND OPERATORS
3.6 DECISIONS AND LOOPS
3.7 HIERARCHICAL DESIGN
3.8 DEBUGGING MODELS
3.9 BASIC DATA TYPES
3.10 SUMMARY
CHAPTER 4: DESIGN AUTOMATION AND TESTING FOR FPGAS
4.1 SIMULATION
4.2 LIBRARIES
4.3 SYNTHESIS
4.4 PHYSICAL DESIGN FLOW
4.5 PLACE AND ROUTE
4.6 TIMING ANALYSIS
4.7 DESIGN PITFALLS
4.8 VHDL ISSUES FOR FPGA DESIGN
4.9 SUMMARY
SECTION 2: APPLICATIONS
CHAPTER 5: INTRODUCTION
CHAPTER 6: IMAGES AND HIGH SPEED PROCESSING
6.1 INTRODUCTION
6.2 THE CAMERA LINK INTERFACE
6.3 GETTING STARTED
6.4 SPECIFYING THE INTERFACES
6.5 DEFINING THE TOP LEVEL DESIGN
6.6 SYSTEM BLOCK DEFINITIONS AND INTERFACES
6.7 THE CAMERALINK INTERFACE
6.8 THE HARD DISC INTERFACE
6.9 SUMMARY
CHAPTER 7: EMBEDDED PROCESSORS
7.1 INTRODUCTION
7.2 A SIMPLE EMBEDDED PROCESSOR
7.3 SOFT CORE PROCESSORS ON AN FPGA
7.4 SUMMARY
SECTION 3: DESIGNER’S TOOLBOX
CHAPTER 8: SERIAL COMMUNICATIONS
8.1 INTRODUCTION
8.2 MANCHESTER ENCODING AND DECODING
8.3 NRZ (NON-RETURN-TO-ZERO) CODING AND DECODING
8.4 NRZI (NON-RETURN-TO-ZERO-INVERTED) CODING AND DECODING
8.5 RS-232
8.6 USB (UNIVERSAL SERIAL BUS)
8.7 SUMMARY
CHAPTER 9: DIGITAL FILTERS
9.1 INTRODUCTION
9.2 CONVERTING S DOMAIN TO Z DOMAIN
9.3 IMPLEMENTING Z DOMAIN FUNCTIONS IN VHDL
9.4 BASIC LOW PASS FILTER MODEL
9.5 FINITE IMPULSE RESPONSE (FIR) FILTERS
9.6 INFINITE IMPULSE RESPONSE (IIR) FILTERS
9.7 SUMMARY
CHAPTER 10: SECURE SYSTEMS
10.1 INTRODUCTION TO BLOCK CIPHERS
10.2 FEISTEL LATTICE STRUCTURES
10.3 THE DATA ENCRYPTION STANDARD (DES)
10.4 ADVANCED ENCRYPTION STANDARD (AES)
CHAPTER 11: MEMORY
11.1 INTRODUCTION
11.2 MODELING MEMORY IN VHDL
11.3 READ ONLY MEMORY (ROM)
11.4 RANDOM ACCESS MEMORY (RAM)
11.5 SYNCHRONOUS RAM (SRAM)
11.6 SUMMARY
CHAPTER 12: PS/2 MOUSE INTERFACE
12.1 INTRODUCTION
12.2 PS/2 MOUSE BASICS
12.3 PS/2 MOUSE COMMANDS
12.4 PS/2 MOUSE DATA PACKETS
12.5 PS/2 OPERATION MODES
12.6 PS/2 MOUSE WITH WHEEL
12.7 BASIC PS/2 MOUSE HANDLER VHDL
12.8 MODIFIED PS/2 MOUSE HANDLER VHDL
12.9 SUMMARY
CHAPTER 13: PS/2 KEYBOARD INTERFACE
13.1 INTRODUCTION
13.2 PS/2 KEYBOARD BASICS
13.3 PS/2 KEYBOARD COMMANDS
13.4 PS/2 KEYBOARD DATA PACKETS
13.5 PS/2 KEYBOARD OPERATION MODES
13.6 BASIC PS/2 KEYBOARD HANDLER VHDL
13.7 MODIFIED PS/2 KEYBOARD HANDLER VHDL
13.8 SUMMARY
CHAPTER 14: A SIMPLE VGA INTERFACE
14.1 INTRODUCTION
14.2 BASIC PIXEL TIMING
14.3 IMAGE HANDLING
14.4 VGA INTERFACE VHDL
14.5 HORIZONTAL SYNC
14.6 VERTICAL SYNC
14.7 HORIZONTAL AND VERTICAL BLANKING PULSES
14.8 CALCULATING THE CORRECT PIXEL DATA
14.9 SUMMARY
SECTION 4: OPTIMIZING DESIGNS
CHAPTER 15: ADVANCED TECHNIQUES
15.1 INTRODUCTION
CHAPTER 16: SYNTHESIS
16.1 INTRODUCTION
16.2 VHDL SUPPORTED IN RTL SYNTHESIS
16.3 SOME INTERESTING CASES WHERE SYNTHESIS MAY FAIL
16.4 WHAT IS BEING SYNTHESISED?
16.5 SUMMARY
CHAPTER 17: BEHAVIOURAL MODELING IN VHDL
17.1 INTRODUCTION
17.2 HOW TO GO FROM RTL TO BEHAVIOURAL VHDL
17.3 SUMMARY
CHAPTER 18: DESIGN OPTIMIZATION
18.1 INTRODUCTION
18.2 TECHNIQUES FOR LOGIC OPTIMIZATION
18.3 IMPROVING PERFORMANCE
18.4 CRITICAL PATH ANALYSIS
18.5 SUMMARY
CHAPTER 19: VHDL-AMS
19.1 INTRODUCTION
19.2 INTRODUCTION TO VHDL-AMS
19.3 ANALOGUE PINS – TERMINALS
19.4 MIXED DOMAIN MODELING
19.5 ANALOGUE VARIABLES – QUANTITIES
19.6 SIMULTANEOUS EQUATIONS IN VHDL-AMS
19.7 A VHDL-AMS EXAMPLE – A DC VOLTAGE SOURCE
19.8 A VHDL-AMS EXAMPLE – RESISTOR
19.9 DIFFERENTIAL EQUATIONS IN VHDL-AMS
19.10 MIXED SIGNAL MODELING WITH VHDL-AMS
19.11 A BASIC SWITCH MODEL
19.12 BASIC VHDL-AMS COMPARATOR MODEL
19.13 MULTIPLE DOMAIN MODELING
19.14 SUMMARY
CHAPTER 20: DESIGN OPTIMIZATION EXAMPLE: DES
20.1 INTRODUCTION
20.2 THE DATA ENCRYPTION STANDARD (DES)
20.3 MOODS
20.4 INITIAL DESIGN
20.5 INITIAL SYNTHESIS
20.6 OPTIMIZING THE DATAPATH
20.7 FINAL OPTIMIZATION
20.8 RESULTS
20.9 TRIPLE DES
20.10 COMPARING THE APPROACHES
20.11 SUMMARY
SECTION 5: FUNDAMENTAL TECHNIQUES
CHAPTER 21: COUNTERS
21.1 INTRODUCTION
21.2 BASIC BINARY COUNTER
21.3 SYNTHESISED SIMPLE BINARY COUNTER
21.4 SHIFT REGISTER
21.5 THE JOHNSON COUNTER
21.6 BCD COUNTER
21.7 SUMMARY
CHAPTER 22: LATCHES, FLIP-FLOPS AND REGISTERS
22.1 INTRODUCTION
22.2 LATCHES
22.3 FLIP-FLOPS
22.4 REGISTERS
22.5 SUMMARY
CHAPTER 23: SERIAL TO PARALLEL & PARALLEL TO SERIAL CONVERSION
23.1 SERIAL TO PARALLEL CONVERSION (SIPO)
23.2 PARALLEL TO SERIAL CONVERSION (PISO)
23.3 SUMMARY
CHAPTER 24: ALU FUNCTIONS
24.1 INTRODUCTION
24.2 LOGIC FUNCTIONS
24.3 1 BIT ADDER
24.4 STRUCTURAL N-BIT ADDITION
24.5 CONFIGURABLE N-BIT ADDITION
24.6 TWOS COMPLEMENT
24.7 SUMMARY
CHAPTER 25: DECODERS AND MULTIPLEXERS
25.1 DECODERS
25.2 MULTIPLEXERS
25.3 SUMMARY
CHAPTER 26: FINITE STATE MACHINES IN VHDL
26.1 INTRODUCTION
26.2 STATE TRANSITION DIAGRAMS
26.3 IMPLEMENTING FINITE STATE MACHINES IN VHDL
26.4 SUMMARY
CHAPTER 27: FIXED POINT ARITHMETIC IN VHDL
27.1 INTRODUCTION
27.2 BASIC FIXED POINT TYPES
27.3 FIXED POINT FUNCTIONS
27.4 TESTING THE FIXED POINT FUNCTION
27.5 SUMMARY
CHAPTER 28: BINARY MULTIPLICATION
28.1 INTRODUCTION
28.2 BASIC BINARY MULTIPLICATION
28.3 VHDL UNSIGNED MULTIPLIER
28.4 SYNTHESIS OF THE MULTIPLICATION FUNCTION
28.5 “SIMPLE” MULTIPLICATION
28.6 SUMMARY
CHAPTER 29: BIBLIOGRAPHY
29.1 INTRODUCTION
29.2 USEFUL TEXTS FOR VHDL AND FPGA DESIGNERS
INDEX
Product details
- No. of pages: 320
- Language: English
- Copyright: © Newnes 2007
- Published: May 11, 2007
- Imprint: Newnes
- eBook ISBN: 9780080548425
About the Authors
Peter Wilson
Peter Wilson is Professor of Electronic Systems Engineering in the Electronic and Electrical Engineering Department at the University of Bath. After obtaining degrees at Heriot-Watt University in Edinburgh he worked as a Senior Design Engineer with Ferranti, Scotland and then as a Technical Specialist for Analogy, Inc. in Oregon, USA. After obtaining his PhD at the University of Southampton, he joined the faculty and was a member of the Academic staff at the University of Southampton from 2002 till 2015 when he moved to the University of Bath. He has published more than 100 papers and 3 books. Peter Wilson is also a Fellow of the IET, Fellow of the British Computer Society, a Chartered Engineer in the UK and a Senior Member of the IEEE.
Affiliations and Expertise
University of Bath and Integra Designs Ltd., UK
Peter Wilson
Peter Wilson is Professor of Electronic Systems Engineering in the Electronic and Electrical Engineering Department at the University of Bath. After obtaining degrees at Heriot-Watt University in Edinburgh he worked as a Senior Design Engineer with Ferranti, Scotland and then as a Technical Specialist for Analogy, Inc. in Oregon, USA. After obtaining his PhD at the University of Southampton, he joined the faculty and was a member of the Academic staff at the University of Southampton from 2002 till 2015 when he moved to the University of Bath. He has published more than 100 papers and 3 books. Peter Wilson is also a Fellow of the IET, Fellow of the British Computer Society, a Chartered Engineer in the UK and a Senior Member of the IEEE.
Affiliations and Expertise
University of Bath and Integra Designs Ltd., UK
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