Advances in Computers
- 1st Edition, Volume 124 - February 4, 2022
- Editor: Suyel Namasudra
- Language: English
- Hardback ISBN:9 7 8 - 0 - 3 2 3 - 8 5 6 8 8 - 1
- eBook ISBN:9 7 8 - 0 - 3 2 3 - 8 5 6 8 9 - 8
Advances in Computers, Volume 124 presents updates on innovations in computer hardware, software, theory, design and applications, with this updated volume including new chapte… Read more
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Request a sales quoteAdvances in Computers, Volume 124 presents updates on innovations in computer hardware, software, theory, design and applications, with this updated volume including new chapters on Traffic-Load-Aware Virtual Channel Power-gating in Network-on-Chips, An Efficient DVS Scheme for On-chip Networks, A Power-Performance Balanced Network-on-Chip for Mixed CPU-GPU Systems, Routerless Networks-on-Chip, Routing Algorithm Design for Power- and Temperature-Aware NoCs, Approximate Communication for Energy-Efficient Network-on-Chip, Power-Efficient NoC Design by Partial Topology Reconfiguration, The Design of a Deflection-based Energy-efficient On-chip Network, and Power-Gating in Networks-on-Chip.
- Contains novel subject matter that is relevant to computer science
- Includes the expertise of contributing authors
- Presents an easy to comprehend writing style
Researchers in high performance computer areas, hardware manufacturers, educational programs in physics and scientific computation and in computer science
- Cover image
- Title page
- Table of Contents
- Copyright
- Contributors
- Preface
- Chapter One: Traffic-load-aware virtual channel power-gating in network-on-chips
- Abstract
- 1: Introduction
- 2: Related work
- 3: Proposed method
- 4: Evaluation
- 5: Conclusion
- References
- Chapter Two: An efficient DVS scheme for on-chip networks
- Abstract
- 1: Introduction
- 2: Motivation and background
- 3: Proposed method
- 4: Evaluation
- 5: Related work
- 6: Conclusion
- References
- Chapter Three: A power-performance balanced network-on-chip for mixed CPU-GPU systems
- Abstract
- 1: Introduction
- 2: Background and motivation
- 3: BiNoCHS architecture
- 4: Evaluation
- 5: Related work
- 6: Conclusion
- References
- Chapter Four: Routerless networks-on-chip
- Abstract
- 1: Introduction
- 2: Background and motivation
- 3: Analysis on wiring resources
- 4: Designing routerless NoCs
- 5: Implementation details
- 6: Evaluation methodology
- 7: Results and analysis
- 8: Discussion
- 9: Conclusion
- References
- Chapter Five: Routing algorithm design for power- and temperature-aware NoCs
- Abstract
- 1: Introduction
- 2: Fundamental of thermal- and traffic-aware NoC
- 3: Thermal-aware proactive routing algorithms in 3D NoCs
- 4: Automated power and thermal management in 2D and 3D NoCs
- 5: Conclusion
- References
- Chapter Six: Approximate communication for energy-efficient network-on-chip
- Abstract
- 1: Introduction
- 2: Related work
- 3: Approximation-based dynamic traffic regulation
- 4: Approximate bufferless network-on-chip
- 5: Approximate multiplane network-on-chip
- References
- Chapter Seven: Power-efficient network-on-chip design by partial topology reconfiguration
- Abstract
- 1: Introduction
- 2: Related work
- 3: NOC architecture
- 4: VAL construction algorithm
- 5: Experimental results
- 6: Conclusions
- References
- Chapter Eight: The design of an energy-efficient deflection-based on-chip network
- Abstract
- 1: Introduction
- 2: Bufferless Routing
- 3: Scalability in mesh-based interconnects
- 4: MinBD: Minimally-buffered deflection router design
- 5: HiRD: Simple hierarchical rings with deflection
- 6: Other methods to improve NoC scalability
- 7: Conclusion and future outlook
- Acknowledgments
- References
- Chapter Nine: Power-gating in NoCs
- Abstract
- 1: Introduction
- 2: Background
- 3: TooT
- 4: SMART
- 5: SPONGE
- 6: MUFFIN
- 7: Evaluation
- 8: Conclusion
- References
- No. of pages: 370
- Language: English
- Edition: 1
- Volume: 124
- Published: February 4, 2022
- Imprint: Academic Press
- Hardback ISBN: 9780323856881
- eBook ISBN: 9780323856898
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Suyel Namasudra
Dr. Suyel Namasudra is an assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Agartala, Tripura, India. Before joining the National Institute of Technology Agartala, Dr. Namasudra was an assistant professor in the Department of Computer Science and Engineering at the National Institute of Technology Patna, Bihar, India, and a post-doctorate fellow at the International University of La Rioja (UNIR), Spain. He has received Ph.D. degree in Computer Science and Engineering from the National Institute of Technology Silchar, Assam, India. His research interests include blockchain technology, cloud computing, IoT, and DNA computing. Dr. Namasudra has edited 4 books, 5 patents, and 60 publications in conference proceedings, book chapters, and refereed journals like IEEE TII, IEEE T-ITS, IEEE TSC, IEEE TCSS, ACM TOMM, ACM TALLIP, FGCS, CAEE, and many more. He has served as a Lead Guest Editor/Guest Editor in many reputed journals like ACM TOMM (ACM, IF: 3.144), CAEE (Elsevier, IF: 3.818), CAIS (Springer, IF: 4.927), CMC (Tech Science Press, IF: 3.772), Sensors (MDPI, IF: 3.576), and many more. Dr. Namasudra has participated in many international conferences as an Organizer and Session Chair. He is a member of IEEE, ACM, and IEI. Dr. Namasudra has been featured in the list of the top 2% scientists in the world in 2021 and 2022, and his h-index is 25.
Affiliations and expertise
Department of Computer Science and Engineering, National Institute of Technology Agartala, Tripura, IndiaRead Advances in Computers on ScienceDirect