VLSI Test Principles and Architectures

Design for Testability

  • Khader S. Abdel-Hafez, SynTest Technologies, Inc.
    • Soumendu Bhattacharya, Georgia Institute of Technology
      • Abhijit Chatterjee, Georgia Institute of Technology
        • Xinghao Chen, City University of New York
          • Kwang-Ting (Tim) Cheng, University of California, Santa Barbara, USA
            • William Eklow, Cisco Systems, Inc.
              • Michael S. Hsiao, Virginia Tech
                • Jiun-Lang Huang, National Taiwan University
                  • Shi-Yu Huang, National Tsing Hua University
                    • Wen-Ben Jone, University of Cincinnati
                      • Rohit Kapur, Synopsys, Inc.
                        • Brion Keller, Cadence Design Systems, Inc.
                          • Kuen-Jong Lee, National Cheng Kung University
                            • James C.-M. Li, National Taiwan University
                              • Mike Peng Li, Wavecrest Corporation
                                • Xiaowei Li, Chinese Academy of Sciences
                                  • T.M. Mak, Intel Corporation
                                    • Yinghua Min, Chinese Academy of Sciences
                                      • Benoit Nadeau-Dostie, LogicVision, Inc.
                                        • Mehrdad Nourani, University of Texas at Dallas
                                          • Janusz Rajski, Mentor Graphics
                                            • Charles Stroud, Auburn University
                                              • Erik H. Volkerink, Agilent Technologies, Inc.
                                                • Duncan M. (Hank) Walker, Texas A&M University
                                                  • Shianling Wu, SynTest Technologies, Inc.
                                                    • Nur Touba, University of Texas, Austin, TX, U.S.A.
                                                    • By

                                                      • Laung-Terng Wang, SynTest Technologies, Inc., Sunnyvale, CA, USA
                                                      • Cheng-Wen Wu, National Tsing Hua University, Hsinchu, Taiwan.
                                                      • Xiaoqing Wen, Kyushu Institute of Technology, Fukuoka, Japan.

                                                      This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
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                                                      Audience

                                                      PRIMARY: Practitioners/Researchers in VLSI Design and Testing; Design or Test Engineers, as well as research institutes.SECONDARY: Undergraduate and graduate-level courses in Electronic Testing, Digital Systems Testing, Digital Logic Test & Simulation, and VLSI Design.

 

Book information

  • Published: July 2006
  • Imprint: MORGAN KAUFMANN
  • ISBN: 978-0-12-370597-6

Reviews

In the era of large systems embedded in a single system-on-chip (SOC) and fabricated continuously shrinking technologies, it is important to ensure correct behavior of the whole system. Electronic design and test engineers of today have to deal with these complex and heterogeneous systems (digital, mixed-signal, memory), but few have the possibility to study the whole field in a detailed and deep way. This book provides an extremely broad knowledge of the discipline, covering the fundamentals in detail, as well as the most recent and advanced concepts. Michel Renovell, Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France This book combines in a unique way insight into industry practices commonly found in commercial DFT tools but not discussed in textbooks, and a sound treatment of the future fundamentals. The comprehensive review of future test technology trends, including self-repair, soft error protection, MEMS testing, and RF testing, leads students and researchers to advanced DFT research. Hans-Joachim Wunderlich, University of Stuttgart, Germany Recent advances in semiconductor manufacturing have made design for testability (DFT) an essential part of nanometer designs. I am pleased to find a DFT textbook of this comprehensiveness that can serve both academic and professional needs. Andre Ivanov, University of British Columbia, Canada This is the most recent book covering all aspects of digital systems testing. It is a “must read” for anyone focused on learning modern test issues, test research, and test practices. Kewal K. Saluja, University of Wisconsin-Madison By covering the basic DFT theory and methodology on digital, memory, as well as analog and mixed-signal (AMS) testing, this book stands out as one best reference book that equips practitioners with testable SOC design skills. Yihe Sun, Tsinghua University, Beijing, China



Table of Contents

Chapter 1 – IntroductionChapter 2 – Design for TestabilityChapter 3 – Logic and Fault Simulation Chapter 4 – Test Generation Chapter 5 – Logic Built-In Self-TestChapter 6 – Test CompressionChapter 7 – Logic DiagnosisChapter 8 – Memory Testing and Built-In Self-TestChapter 9 – Memory Diagnosis and Built-In Self-RepairChapter 10 – Boundary Scan and Core-Based TestingChapter 11 – Analog and Mixed-Signal TestingChapter 12 – Test Technology Trends in the Nanometer Age