Networks on Chips book cover

Networks on Chips

Technology and Tools


Published: February 2006

Imprint: Morgan Kaufmann

ISBN: 978-1-4933-0082-2


  • “The design of a complex SoC requires the mastering of two major tasks: The design of the computational elements and of their interconnect. The exponentially increasing complexity and heterogeneity of future SoCs forces the designer to abandon traditional bus -based structures and to implement innovative networks-on-chip. This book, written by two leading researchers, is the first of its kind. It is a must on the bookshelf of anybody having an interest in SoC design.” — Heinrich Meyr, Professor RWTH Aachen University and Chief Scientific officer, CoWare, Inc. “This is a highly recommended, informative reference book, with high quality contents provided by the leading experts of the area.” — Professor Bashir M. Al-Hashimi, Electronic Systems Design Group, Department of Electronics and Computer Science, University of Southampton, UK “An in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions, make this book a reference for engineers involved in specification, design or evaluation of NoC architectures.” —Philippe Martin, Product Marketing Director, Arteris “Designers of Systems-on-a-Chip (SoC) are now struggling with the uncertainty of deep submicron devices and an explosion of system complexity. Networks on Chip (NoC) is a new paradigm of SoC design at the system architecture level. A protocol stack of NoC introduced in this book shows a global solution to manage the complicated design problems of SoC. This book gives a clear and systematic methodology of NoC design and will release designers from the nightmare of fights against signal integrity, reliability and variability.” — Hiroto Yasuura, Director and Professor, System LSI Research Center (SLRC), Kyushu University, Fukuoka, Japan


  • I. Introduction and Motivation Why on chip networks? State of the artTaxonomyTechnology trends II. Architectures for NoCsDirect vs indirect networksTopologiesStandard architectures and formal propertiesAd hoc networks III. Physical network layer Wiring issuesPhysical routingSignallingDriver/receiver designNoise immunityShieldingIV. Data-link layer and encoding Medium access controlData encodingError correcting codes: theory and practiceArbitration issuesV. Switching and Routing in NoCs Packets, flits.Data forwarding schemesRouting: algorithms and routers QoS guaranteesVI. Software for NoCsProgramming paradigms: shared medium vs message passingMiddleware issues. layering and software encapsulationApplication layer issue and network-aware compilationVII. Tools for NoC Design Analysis and Synthesis of NoCsPresent tools (Bones, Xpipes) and future outlookVIII. On-Chip multiprocessors High-performance monolithic multiprocessorsNetwork issuesIX. SoCs based on NoCsExamples of other design chips using NoCs


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