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| LOW POWER DESIGN FOR MICROPROCESSORS AND SYSTEM ON CHIP
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Nanometer and System-Level Design
To order this title, and for more information, click here
By
Subhomoy Chattopadhyay, IMD
Rakesh Patel
Audience
Designers of Microprocessors and Systems-on-Chip (SOC), concerned with power consumption, at companies globally such as Intel, AMD, IBM,
HP, NVIDIA, Marvell, Texas Instruments, Samsung, Hitachi, Sony, Fujitsu, Toshiba, ST Microelectronics, NXP, Freescale, Infineon, NOKIA,
Qualcom, etc.
Contents
Introduction to the Importance of Low Power Design; Architectural Optimization for Level Low Power System Design; Platform power estimation
and Optimization; Low Power Logic Design Techniques; MOS Device Design and Implications on Low Power Design; Low Power Memory/SRAM Architecture
and Design; Average power/Leakage Power Reduction Techniques; Dynamic/Active Power Reduction Techniques; Low Power Estimation techniques
(Short Circuit, leakage and Active power); Low Power Estimation and Optimization Tools – Overview; Power Consideration for Reliability
and Power-grid design.
| Bibliographic details |
e-Book, 400 pages, publication date: JUN-2009
ISBN-13: 978-0-08-092094-8
Imprint: MORGAN KAUFFMAN
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| Price and Ordering |
Price:
USD 79.95
EUR 66.95
GBP 45.99
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077/745
Last update: 25 Nov 2009
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