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By
Vasilis Pavlidis
Eby Friedman
Description
With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing
the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance
among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.
Three-dimensional
(3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance
and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck"
challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However,
before these advantages can be realized, key technology challenges of 3D ICs must be addressed.
This is the first book on 3-D
integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective
solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference
or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.
Audience
VLSI design engineers, CAD Designers of Microprocessors and Systems-on-Chip (SOC), concerned with 3-D integration in chip design...INTERCONNECT,
at companies globally such as Microsoft, Honeywell, Intel, AMD, IBM, HP, NVIDIA, Marvell, Texas Instruments, Samsung, Hitachi, Sony,
Fujitsu, Toshiba, ST Microelectronics, NXP, Freescale, Infineon, NOKIA, Qualcom, Cadence, Synopsys, Magma, Mentor Graphics, Tezzaron
Inc, Ziptronix,
Tru-Si, IMEC Belgium, etc.
Contents
Chapter 1. Introduction
1.1. From the Integrated Circuit to the Computer
1.2. Interconnects; an old Friend
1.3. Three-Dimensional
or Vertical Integration
1.3.1. Opportunities for Three-Dimensional Integration
1.3.2. Challenges for Three-Dimensional Integration
1.4. Book Organization
Chapter 2. Manufacturing of 3-D Packaged Systems
2.1. Three-Dimensional Integration
2.1.1. System-in-Package
2.1.2. Three-Dimensional Integrated Circuits
2.2. System-on-Package
2.3. Technologies for System-in-Package
2.3.1. Wire
Bonded System-in-Package
2.3.2. Peripheral Vertical Interconnects
2.3.3. Area Array Vertical Interconnects
2.3.4. Metallizing
the Walls of an SiP
2.4. Cost Issues for 3-D Integrated Systems
2.5. Summary
Chapter 3. 3-D Integrated Circuit Fabrication Technologies
3.1. Monolithic 3-D ICs
3.1.1. Stacked 3-D ICs
3.1.2. 3-D Fin-FETs
3.2. 3-D ICs with Through Silicon (TSV) or Interplane
Vias
3.3. Contactless 3-D ICs
3.3.1. Capacitively Coupled 3-D ICs
3.3.2. Inductively Coupled 3-D ICs
3.4. Vertical Interconnects
for 3-D ICs
3.4.1. Electrical Characteristics of Through Silicon Vias
3.5. Summary
Chapter 4. Interconnect Prediction Models
4.1. Interconnect Prediction Models for 2-D Circuits
4.2. Interconnect Prediction Models for 3-D ICs
4.3. Projections for
3-D ICs
4.4. Summary
Chapter 5. Physical Design Techniques for 3-D ICs
5.1. Floorplanning Techniques
5.1.1. Single versus
Multi-Step Floorplanning for 3-D ICs
5.1.2. Multi-Objective Floorplanning Techniques for 3-D ICs
5.2. Placement Techniques
5.2.1. Multi-Objective Placement for 3-D ICs
5.3. Routing Techniques
5.4. Layout Tools
5.5. Summary
Chapter 6. Thermal Management
Techniques
6.1. Thermal Analysis of 3-D ICs
6.1.1. Closed-Form Temperature Expressions
6.1.2. Compact Thermal Models
6.1.3. Mesh Based Thermal Models
6.2. Thermal Management Techniques without Thermal Vias
6.2.1. Thermal-Driven Floorplanning
6.2.2. Thermal-Driven Placement
6.3. Thermal Management Techniques Employing Thermal Vias
6.3.1. Region Constrained Thermal
Via Insertion
6.3.2. Thermal Via Planning Techniques
6.3.3. Thermal Wire Insertion
6.4. Summary
Chapter 7. Timing Optimization
for Two-Terminal Interconnects
7.1. Interplane Interconnect Models
7.2. Two-Terminal Nets with a Single Interplane Via
7.2.1.
Elmore delay model of an interplane interconnect
7.2.2. Interplane Interconnect Delay
7.2.3. Optimum Via Location
7.2.4. Improvement
in Interconnect Delay
7.3. Two-Terminal Interconnects with Multiple Interplane Vias
7.3.1. Two-Terminal Via Placement Heuristic
7.3.2. Two-Terminal Via Placement Algorithm
7.3.3. Application of the Via Placement Technique
7.4. Summary
Chapter 8. Timing
Optimization for Multi-Terminal Interconnects
8.1. Timing-Driven Via Placement for Interplane Interconnect Trees
8.2. Multi-Terminal
Interconnect Via Placement Heuristics
8.2.1. Interconnect Trees
8.2.2. Single Critical Sink Interconnect Trees
8.3. Via Placement
Algorithms for Interconnect Trees
8.3.1. Interconnect Tree Via Placement Algorithm (ITVPA)
8.3.2. Single Critical Sink Interconnect
Tree Via Placement Algorithm (SCSVPA)
8.4. Via Placement Results and Discussion
8.5. Summary
Appendix A:Enumeration of Gate
Pairs in a 3-D IC
Appendix B:Formal Proof of Optimum Single Via Placement
Appendix C:Proof of the Two-Terminal Via Placement Heuristic
Appendix D:Proof of Condition for Via Placement of Multi-Terminal Nets
References
| Bibliographic details |
Hardbound, 336 pages, publication date: SEP-2008
ISBN-13: 978-0-12-374343-5
Imprint: MORGAN KAUFFMAN
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EUR 56.95
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Last update: 25 Nov 2009
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