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Synthesis, Verification, and Test
To order this title, and for more information, click here
Edited By
Laung-Terng Wang, SynTest Technologies, Inc., Sunnyvale, CA, USA
Yao-Wen Chang, National Taiwan University, Taipai, Taiwan
Kwang-Ting Cheng, University of California, Santa Barbara, USA
Included in series
Systems on Silicon,
Description
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency
in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and
architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures,
algorithms, and architectures of the EDA flow will benefit from this book.
Audience
Practitioners/Researchers in electronic design automation, including VLSI design engineers, verfication engineers, and test engineers.
Contents
Introduction; Fundamentals of CMOS Design; Design for Testability; Fundamentals of Algorithms; Electronic System-Level Design and Modeling;
High-Level Synthesis; Logic Synthesis; Test Synthesis; Logic and Circuit Simulation; Functional Verification; Floorplanning; Placement;
Global and Detailed Routing; Synthesis of Clock and Power/Ground Networks; Fault Simulation and Test Generation.
| Bibliographic details |
Hardbound, 972 pages, publication date: FEB-2009
ISBN-13: 978-0-12-374364-0
Imprint: MORGAN KAUFFMAN
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| Price and Ordering |
Price:
USD 89.95
EUR 63.95
GBP 54.99
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Last update: 5 Sep 2009
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