System-on-Chip Test Architectures

Nanometer Design for Testability

System-on-Chip Test Architectures on ScienceDirect(Opens new window)
Hardbound, 896 Pages
Published: NOV-2007
ISBN 10: 0-12-373973-X
ISBN 13: 978-0-12-373973-5
Imprint: MORGAN KAUFMANN


By
Laung-Terng Wang, SynTest Technologies, Inc., Sunnyvale, CA, USA
Charles Stroud, Auburn University, Auburn, AL, U.S.A.
Nur Touba, University of Texas, Austin, TX, U.S.A.

Description
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Included in series
Systems on Silicon

Audience:
Practitioners/Researchers in VLSI Design and Testing; Design or Test Engineers, as well as research institutes.


 
Last update: 6 Nov 2011