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The Theory and Practice of FPGA-Based Computation
To order this title, and for more information, click here
By
Scott Hauck, Associate Professor, University of Washington, Department of Electrical Engineering, Seattle, WA, U.S.A.
André DeHon, Assistant Professor, Computer Science, California Institute of Technology, Pasadena, CA, USA.
Included in series
Systems on Silicon,
Audience
Primary: Researchers/Practitioners in Reconfigurable Computing and FPGAs.
Secondary: Graduate-level courses in Advanced Digital Systems
(digital design), Reconfigurable Computing, Advanced Computer Architecture, Digital Signal Processing.
Contents
Contents
Preface
Introduction
Part One: Hardware
Part I INTRO
Chapter 1 - General-Purpose FPGA Architecture
Chapter 2 - Reconfigurable
Computing Devices
Chapter 3 - Reconfigurable Computing Systems
Chapter 4 - Reconfiguration Management
Part Two: Software
Part II Intro
Chapter 5 - Computer Models and System Architectures
Andre DeHon Chapter 6 - Hardware Description Languages (VHDL)
Chapter 7 - Compilation
for Reconfigurable Computing Machines
Chapter 8 - Streaming Models
8.1 MATLAB/SIMULINK
8.2 SCORE
Chapter 9 SIMD/Vector
Chapter 10 -
OS/Runtime Systems
Chapter 11 - JHDL
Chapter 12 -Technology Mapping
Chapter 13 - Placement
13.1 General-purpose / FPGA
13.2 Datapath
13.3 Constructive
Chapter 14 - Routing
Chapter 15 - Retimin
Chapter 16 - Bitstream Generation, JBits
Chapter 17 - Fast Mapping
Part
Three: Application Development
PART III INTROChapter 18 - Evaluating and Optimizing problems for FPGA implementations
Chapter 19- Instance-specific
design, Constant Propagation & Partial Evaluation
Chapter 20 - Precision Analysis & Floating Point
Chapter 21 - Distributed Arithmetic
Chapter 22 - CORDIC
Chapter 23 - Task allocation: FPGA vs. CPU partitioning
Part Four: Case Studies
PART IV INTRO
Chapter 24 - Image
Processing, Variable Precision, Algorithm Alteration: SPIHT Compression
Chapter 25 - Run-time reconfiguration: Automatic Target Recognition
Chapter 26 - Problem-specific circuitry: SAT Solving
Chapter 27 - Multi-FPGA Systems: Logic Emulation
Chapter 28- Floating Point
Chapter
29 - FDTD
Chapter 30 - Genetic Evolution
Chapter 31 - Packet Filtering (Networking application)
Chapter 32 - Active Pages [Memory centric]
Part Five: Theoretical Underpinnings and Future Directions
PART V INTRO
Chapter 33- Theoretical Underpinnings, Metrics and Analysis
Chapter 34 - Defect and Fault Tolerance
Chapter 35 - Reconfigurable Computing and Nanotechnology
| Bibliographic details |
Hardbound, 944 pages, publication date: NOV-2007
ISBN-13: 978-0-12-370522-8
ISBN-10: 0-12-370522-3
Imprint: MORGAN KAUFFMAN
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GBP 52
USD 83.95
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Last update: 13 Jun 2009
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