 |
|
| VERIFICATION TECHNIQUES FOR SYSTEM-LEVEL DESIGN
| |
| | |
|
|
To order this title, and for more information, click here
By
Masahiro Fujita, Professor, VLSI Design & Education Center, University of Tokyo, Japan.
Indradeep Ghosh, Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.
Mukul Prasad, Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.
Included in series
Systems on Silicon,
Audience
PRIMARY: Practitioners/Researchers in System-Level Design and Verification; Design Engineers at companies such as Synopsis, Cadence, Intel.
SECONDARY: Reference for graduate-level courses in SoC design and verification.
| Bibliographic details |
Hardbound, 256 pages, publication date: OCT-2007
ISBN-13: 978-0-12-370616-4
ISBN-10: 0-12-370616-5
Imprint: MORGAN KAUFFMAN
|
| Price and Ordering |
Price:
EUR 60.95
GBP 52
USD 83.95
|  |
Books and book related electronic products are priced in US dollars (USD), euro (EUR), and Great Britain Pounds (GBP). USD prices apply to the Americas and Asia Pacific. EUR prices apply in Europe and the Middle East. GBP prices apply to the UK and all other countries.
|
See also information about conditions of sale & ordering procedures, and links to our regional sales offices.
|
077/745
Last update: 5 Sep 2009
|
|
| |
| | |
|
|
| |
Home | Elsevier Sites | Privacy Policy | Terms and Conditions | Feedback | Site Map | A Reed Elsevier Company