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| VLSI TEST PRINCIPLES AND ARCHITECTURES
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Design for Testability
To order this title, and for more information, click here
By
Laung-Terng Wang, SynTest Technologies, Inc., Sunnyvale, CA, USA
Cheng-Wen Wu, National Tsing Hua University, Hsinchu, Taiwan.
Xiaoqing Wen, Kyushu Institute of Technology, Fukuoka, Japan.
Included in series
Systems on Silicon,
Description
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down
test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
Audience
PRIMARY: Practitioners/Researchers in VLSI Design and Testing; Design or Test Engineers, as well as research institutes.
SECONDARY: Undergraduate
and graduate-level courses in Electronic Testing, Digital Systems Testing, Digital Logic Test & Simulation, and VLSI Design.
Contents
Chapter 1 – Introduction
Chapter 2 – Design for Testability
Chapter 3 – Logic and Fault Simulation
Chapter 4 – Test Generation
Chapter
5 – Logic Built-In Self-Test
Chapter 6 – Test Compression
Chapter 7 – Logic Diagnosis
Chapter 8 – Memory Testing and Built-In Self-Test
Chapter 9 – Memory Diagnosis and Built-In Self-Repair
Chapter 10 – Boundary Scan and Core-Based Testing
Chapter 11 – Analog and Mixed-Signal
Testing
Chapter 12 – Test Technology Trends in the Nanometer Age
| Bibliographic details |
Hardbound, 808 pages, publication date: JUL-2006
ISBN-13: 978-0-12-370597-6
ISBN-10: 0-12-370597-5
Imprint: MORGAN KAUFMANN
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| Price and Ordering |
Price:
EUR 51.95
USD 77.95
GBP 47.99
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Last update: 30 Jan 2010
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