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| ASIC AND FPGA VERIFICATION
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A Guide to Component Modeling
To order this title, and for more information, click here
By
Richard Munden, CEO, Free Model Foundry
Included in series
Systems on Silicon,
Description
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use
off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that
are required for accurate verification of today?s digital designs.
ASIC and FPGA Verification: A Guide to Component Modeling expertly
illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer
who simulates multi-chip digital designs.
Audience
Digital system designers and industry short courses focused on component modeling
Contents
1.Introduction to Board-Level Verification; 2.Tour of a simple model; 3.VHDL packages for component models; 4.Introduction to SDF; 5.Anatomy
of a VITAL Model; 6.Modeling Delays; 7.VITAL truth tables; 8.Modeling timing constraints; 9.Modeling registered devices; 10.Conditional
delays and timing constraints; 11.Negative timing constraints; 12.Timing Files and Backannotation; 13.Adding Timing to Your RTL Code;
14.Modeling Memories; 15.Considerations for Component Modeling; 16.Modeling Component Centric Features; 17.Testbenches for Component
Models
| Bibliographic details |
Paperback, 336 pages, publication date: SEP-2004
ISBN-13: 978-0-12-510581-1
ISBN-10: 0-12-510581-9
Imprint: MORGAN KAUFFMAN
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| Price and Ordering |
Price:
EUR 46.95
GBP 40
USD 62.95
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Last update: 5 Sep 2009
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