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By Parag Lala, North Carolina Agricultural and Technical State University
Description
With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased
complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing
strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips,
fault-tolerant, self-checking mechanisms must be built in to assure reliable operation.
Self-Checking and Fault-Tolerant Digital
Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware
fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of
the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems.
Contents
Chapter 1 - Fundamentals of Reliability
1.1 Reliability and Failure Rate
1.2 Relation between Reliability and Mean-Time-Between-Failures
1.3 Maintainability
1.4 Availability
1.5 Series and Parallel Systems
1.6 Dependability
References
Chapter 2 - Error Detecting
and Correcting Codes
2.1 Parity Code
2.2 Multiple Error Detecting Codes
2.2.1 Unordered Codes for Unidirectional Error Detection
m-out-of-n Codes Berger Code
2.2.2 t-unidirectional Error Detecting Codes
Borden Code
Bose-Lin Codes
2.2.3 Burst Unidirectional
Error Detecting Code
2.3 Residue Codes
2.4 Cyclic Codes
2.5 Error-Correcting Codes
2.5.1 Hamming Code
2.5.2 Hsiao Code
2.5.3
Reed-Solomon Code
References
Chapter 3 - Self-Checking Combinational Logic Design
3.1 Strongly Fault-secure Circuits
3.2
Strongly Code-disjoint Circuits
3.3 Terminology
3.4 Bidirectional Error Free Combinational Circuit Design
3.5 Detection of Input Fault
Induced Bidirectional Errors
3.6 Techniques for Bidirectional Error Elimination
3.6.1 Input Encoding
3.6.2 Output Encoding
3.7
Self-dual Parity Checking
3.8 Self-Checking Design using Low-Cost Residue Code
3.9 Totally Self-Checking PLA Design
3.10 Fail-safe
Combinational Circuit Design
References
Chapter 4 - Self-Checking Checkers
4.1 The Two-rail Checker
4.2 Totally Self-Checking
Checkers for m-out-of-n codes
4.2.1 Pass Transistor-based Checker Design for a subset of m-out-of-2m codes
4.2.2 Totally Self-Checking
Checker for I-out-of-n-code
4.3 Totally Self-Checking Checkers for Berger code
4.4 Totally Self-Checking Checkers for Low-cost Residue
code
References
Chapter 5 - Self-Checking Sequential Circuit Design
5.1 Faults in State Machines
5.2 Self-Checking State Machine
Design Techniques
5.3 Elimination of Bidirectional Errors
5.4 Synthesis of Redundant Fault-free State Machines
5.5 Decomposition of
Finite State Machines
5.6 Self-Checking Interacting State Machine Design
5.7 Fail-safe State Machine Design
References
Chapter
6 - Fault-Tolerant Design
6.1 Hardware Redundancy
6.1.1 Static Redundancy
Triple Modular Redundancy
6.1.2 Dynamic Redundancy
6.1.3 Hybrid redundancy
6.2 Information Redundancy
6.2.1 Fault-tolerant state machine design using Hamming codes
6.2.2 Error Checking
and Correction (ED) in Memory Systems
6.2.3 Improvement in Reliability with ECC
6.2.4 Multiple Error Correction using Orthogonal Latin
Square Configuration
6.2.5 Soft error Correction using Horizontal and Vertical Parity Method
6.3 Time Redundancy
6.4 Software Redundancy
6.5 System Level Fault Tolerance
6.5.1 Byzantine Fault Model
6.5.2 System Level Fault Detection
6.5.3 Backward Recovery Schemes
6.5.4 Forward Recovery Schemes References
References
Appendix
Markov Models
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