Verification Techniques for System-Level Design

Verification Techniques for System-Level Design on ScienceDirect(Opens new window)
Hardbound, 256 Pages
Published: OCT-2007
ISBN 10: 0-12-370616-5
ISBN 13: 978-0-12-370616-4
Imprint: MORGAN KAUFMANN


By
Masahiro Fujita, Professor, VLSI Design & Education Center, University of Tokyo, Japan.
Indradeep Ghosh, Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.
Mukul Prasad, Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.

Included in series
Systems on Silicon

Audience:
PRIMARY: Practitioners/Researchers in System-Level Design and Verification; Design Engineers at companies such as Synopsis, Cadence, Intel.SECONDARY: Reference for graduate-level courses in SoC design and verification.


 
Last update: 6 Nov 2011