VHDL Coding and Logic Synthesis with Synopsys - 1st Edition - ISBN: 9780124406513, 9780080520506

VHDL Coding and Logic Synthesis with Synopsys

1st Edition

Authors: Weng Fook Lee
Hardcover ISBN: 9780124406513
eBook ISBN: 9780080520506
Imprint: Academic Press
Published Date: 24th July 2000
Page Count: 392
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Description

List of Figures. List of Tables. List of Examples. Preface. Acknowledgement. Trademarks.

I. VHDL CODING

  1. Introduction. 1.1 Conventional Design - Schematic Capture 1.2 Hardware Description Language 1.3 VHDL Design Structure 1.4 Component Instantiation Within a VHDL Design Structure 1.5 Structural, Behavioral, and Synthesizable VHDL Design Structure 1.5.1 Structural VHDL 1.5.2 Behavioral VHDL 1.5.3 RTL Code 1.6 Usage of Library Declarations in VHDL Design Structure

  2. VHDL Simulation and Synthesis Flow.

  3. Synthesizable Code for Basic Logic Components. 3.1 AND Logic 3.2 OR Logic 3.3 NOT Logic 3.4 NAND Logic 3.5 NOR Logic 3.6 Tristate Buffer Logic 3.7 Complex Logic Gate 3.8 Latch 3.8.1 Acoiding Latches In Your Code 3.9 Flip Flop 3.10 Decoder 3.11 Encoder 3.12 Multiplexer 3.13 Priority Encoder 3.14 Memory Cell 3.15 Adder 3.16 Component Inference

  4. Signal Versus Variable. 4.1 Variable 4.2 Signal 4.3 When to Use Signal and When to Use Variable 4.4 Usage of Loopback Signal

  5. Examples of Complex Synthesizable Code. 5.1 Shifter 5.2 Counter 5.3 Memory Module 5.4 Car Traffic Controller

  6. Pipeline Microcontroller Synthesizable Design. 6.1 Intruction Set Definition 6.2 Architechtural Definition 6.3 Pipeline Definition 6.4 Microarchitechture Definition for the Pipeline Microcontroller 6.4.1 Predecode Block 6.4.2 Decode Block 6.4.3 Register File Block 6.4.4 Execute Block

II. LOGIC SYNTHESIS WITH SYNOPSYS.

  1. Timing Considerations in Design. 7.1 Setup Timing Violation 7.2 Hold Timiing Violation 7.3 Setup/Hold Timing Considerations in Synthesis 7.4 Microarchitechural Tweaks for Fixing Setup Time Violations 7.4.1 Logic Duplication to Generate Independent Paths 7.4.2 Logic Duplication Prior to Selection of Later Arrival Signal 7.4.3 Balancing of Logic between Flip-Flops 7.4.4 Priority Decoding Versus Multiplex Decoding 7.5 Microarchitechtural Tweaks for Fixing Hold Time Violations 7.6 Asynchronous/False Paths 7.7 Multicycle Paths

  2. VHDL Synthesis with Timing Constraints. 8.1 Introduction to Design Compiler 8.2 IUsing Design Compiler for Synthesis 8.3 Performance Tweaks 8.3.1 Compilation With 'map_effort high' Option 8.3.2 Group Critical Paths Together and Give Them a Weight Factor 8.3.3 Logical Flattening of a Design 8.3.4 Characterizing Submodules 8.3.5 Register Balancing 8.3.6 Usage of FSM Compiler to Optimize Finite State Machine 8.3.7 Choosing High-Speed Implementation for High-Level Functional Module 8.3.8 Balancing of Logic Trees with Heavy Loading 8.4 Area Optimization in Synthesis Tweaks 8.4.1 Do Not Use Combinational Logic as Individual Blocks 8.4.2 Do Not Use Glue Logic between Modules 8.4.3 set_max_area Attribute 8.5 Fixing Hold-Time Violations in Synopsys 8.6 Misc Synthesis Commands Generally Used 8.7 Top-Down and Bottoms-Up Compilation

  3. GTECH Instantiation.

  4. DesignWare Library. 10.1 Creating Your Own Designware Library

  5. Testability Issues in Synthesis. 11.1 Multiplexed Flip-Hop Scan Style 11.2 Using Synopsys Test Compiler for Scan Insertion

  6. FPGA Synthesis.

  7. Synthesis Links to Layout. 13.1 Forward-Annotations 13.2 Wireload Models 13.3 Floorplanning a Design 13.4 Post Layout Optimization

  8. Design Guideline to Follow for Efficient Synthesis.

  9. Appendix A (STD_LOGIC_1164 Library).

  10. Appendix B (Shifter Synthesis Results).

  11. Appendix C (Counter Synthesis Results).

  12. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation).

  13. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6).

  14. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6).

Glossary.

Bibliography.

Index.

Key Features

@bul:* First practical guide to using synthesis with Synopsys

  • Synopsys is the #1 design program for IC design

Readership

Electrical and computer engineering students and professionals in microelectronics and circuit design.

Table of Contents

List of Figures. List of Tables. List of Examples. Preface. Acknowledgement. Trademarks.

I. VHDL CODING

  1. Introduction. 1.1 Conventional Design - Schematic Capture 1.2 Hardware Description Language 1.3 VHDL Design Structure 1.4 Component Instantiation Within a VHDL Design Structure 1.5 Structural, Behavioral, and Synthesizable VHDL Design Structure 1.5.1 Structural VHDL 1.5.2 Behavioral VHDL 1.5.3 RTL Code 1.6 Usage of Library Declarations in VHDL Design Structure

  2. VHDL Simulation and Synthesis Flow.

  3. Synthesizable Code for Basic Logic Components. 3.1 AND Logic 3.2 OR Logic 3.3 NOT Logic 3.4 NAND Logic 3.5 NOR Logic 3.6 Tristate Buffer Logic 3.7 Complex Logic Gate 3.8 Latch 3.8.1 Acoiding Latches In Your Code 3.9 Flip Flop 3.10 Decoder 3.11 Encoder 3.12 Multiplexer 3.13 Priority Encoder 3.14 Memory Cell 3.15 Adder 3.16 Component Inference

  4. Signal Versus Variable. 4.1 Variable 4.2 Signal 4.3 When to Use Signal and When to Use Variable 4.4 Usage of Loopback Signal

  5. Examples of Complex Synthesizable Code. 5.1 Shifter 5.2 Counter 5.3 Memory Module 5.4 Car Traffic Controller

  6. Pipeline Microcontroller Synthesizable Design. 6.1 Intruction Set Definition 6.2 Architechtural Definition 6.3 Pipeline Definition 6.4 Microarchitechture Definition for the Pipeline Microcontroller 6.4.1 Predecode Block 6.4.2 Decode Block 6.4.3 Register File Block 6.4.4 Execute Block

II. LOGIC SYNTHESIS WITH SYNOPSYS.

  1. Timing Considerations in Design. 7.1 Setup Timing Violation 7.2 Hold Timiing Violation 7.3 Setup/Hold Timing Considerations in Synthesis 7.4 Microarchitechural Tweaks for Fixing Setup Time Violations 7.4.1 Logic Duplication to Generate Independent Paths 7.4.2 Logic Duplication Prior to Selection of Later Arrival Signal 7.4.3 Balancing of Logic between Flip-Flops 7.4.4 Priority Decoding Versus Multiplex Decoding 7.5 Microarchitechtural Tweaks for Fixing Hold Time Violations 7.6 Asynchronous/False Paths 7.7 Multicycle Paths

  2. VHDL Synthesis with Timing Constraints. 8.1 Introduction to Design Compiler 8.2 IUsing Design Compiler for Synthesis 8.3 Performance Tweaks 8.3.1 Compilation With 'map_effort high' Option 8.3.2 Group Critical Paths Together and Give Them a Weight Factor 8.3.3 Logical Flattening of a Design 8.3.4 Characterizing Submodules 8.3.5 Register Balancing 8.3.6 Usage of FSM Compiler to Optimize Finite State Machine 8.3.7 Choosing High-Speed Implementation for High-Level Functional Module 8.3.8 Balancing of Logic Trees with Heavy Loading 8.4 Area Optimization in Synthesis Tweaks 8.4.1 Do Not Use Combinational Logic as Individual Blocks 8.4.2 Do Not Use Glue Logic between Modules 8.4.3 set_max_area Attribute 8.5 Fixing Hold-Time Violations in Synopsys 8.6 Misc Synthesis Commands Generally Used 8.7 Top-Down and Bottoms-Up Compilation

  3. GTECH Instantiation.

  4. DesignWare Library. 10.1 Creating Your Own Designware Library

  5. Testability Issues in Synthesis. 11.1 Multiplexed Flip-Hop Scan Style 11.2 Using Synopsys Test Compiler for Scan Insertion

  6. FPGA Synthesis.

  7. Synthesis Links to Layout. 13.1 Forward-Annotations 13.2 Wireload Models 13.3 Floorplanning a Design 13.4 Post Layout Optimization

  8. Design Guideline to Follow for Efficient Synthesis.

  9. Appendix A (STD_LOGIC_1164 Library).

  10. Appendix B (Shifter Synthesis Results).

  11. Appendix C (Counter Synthesis Results).

  12. Appendix D (Pipeline Microcontroller Synthesis Results--Top-Down Compilation).

  13. Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6).

  14. Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6).

Glossary.

Bibliography.

Index.

Details

No. of pages:
392
Language:
English
Copyright:
© Academic Press 2000
Published:
Imprint:
Academic Press
eBook ISBN:
9780080520506

About the Author

Weng Fook Lee

Weng Fook Lee is a distinguished principal design engineer at Advanced Micro Devices, Inc. (AMD) and has earned the reputation as a respected synthesis expert. He has vast experience designing ASIC with VHDL. He is an expert at synthesizing circuits tweaked for maximum performance and minimal area utilization, and at developing and implementing new synthesis, verification, and auto place and route design methodology. WF Lee is deeply involved in the design and synthesis of PCI, ISA, and LPC bridges, chipsets, microcontrollers, RISC microprocessors, and state-of-the-art, high-speed, low-power flash memory.

Affiliations and Expertise

Advanced Micro Devices, Inc. (AMD)