VHDL 101 - 1st Edition - ISBN: 9781856177047, 9780080959399

VHDL 101

1st Edition

Everything you Need to Know to Get Started

Authors: William Kafig
eBook ISBN: 9780080959399
Paperback ISBN: 9781856177047
Imprint: Newnes
Published Date: 22nd December 2010
Page Count: 200
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Description

VHDL 101 is written for Electrical Engineers and others wishing to break into FPGA design and assumes a basic knowledge of digital design and some experience with engineering ‘process’.

Bill Kafig, industry expert, swiftly brings the reader up to speed on techniques and functions commonly used in VHDL (VHSIC Hardware Description Language) as well as commands and data types. Extensive simple, complete designs accompany the content for maximum comprehension. The book concludes with a section on design re-use, which is of utmost importance to today's engineer who needs to meet a deadline and lower costs per unit.

Gets you up to speed with VHDL fast, reducing time to market and driving down costs

Covers the basics including language concepts and includes complete design examples for ease of learning

Covers widely accepted industry nomenclature

Learn from "best design practices"

Key Features

  • Gets you up to speed with VHDL fast, reducing time to market and driving down costs
  • Covers the basics including language concepts and includes complete design examples for ease of learning
  • Covers widely accepted industry nomenclature
  • Learn from "best design practices"

Readership

Electrical engineers, hardware engineers, and students that have no FPGA or VHDL experience

Table of Contents

Preface; About the Author; Acknowledgments; Chapter 1: Introduction and Background, 1.1 VHDL, Brief History of VHDL, 1.2.1 Coding Styles: Structural vs. Behavioral vs. RTL, 1.3 FPGA Architecture, 1.3.1 Creating the Design; Chapter 2: Overview of the Process of Implementing an FPGA Design, 2.1 Design Entry, Synthesis, 2.3 Simulation. 2.4 Implementation, 2.4.1 Translate, 2.4.2 Map, 2.4.3 Place and Route, 2.5. Bitstream Generation;Chapter 3: Loop 1 - Going with the Flow, 3.1 The Shape of VHDL, 3.1.1 The Many Levels of Comments, 3.1.2 Library and Package Inclusion, 3.1.3 Entity, 3.1.4 Architecture, 3.1.5 Configuration Statements, 3.1.6 Signals, Data Types, Logical Operators, 3.1.7 Concurrent Statements, 3.1.8 Baud Rate Generator, 3.1.9 Transmitter, 3.1.10 Receiver, 3.1.11 Introducing the Simulation Environment; Chapter 4: Loop 2 - Going Deeper, 4.1 Introducing Processes, Variables, and Sequential Statements, 4.1.1 Variables, 4.1.2 Signals within processes, 4.1.3 Sequential Statements, 4.2 Tool Perspectives - Synthesis Options and Contraints, 4.2.1 Synthesis Options, 4.2.2 Constraints; Chapter 5: Loop 3, 5.1 Introducing Concept of Reuse, 5.1.1 A Little More on Libraries and Packages, 5.2 Flexibility Using Generics and Constants, 5.3 Generate Statements, 5.3.1 Conditional Generate Form, 5.3.2 Generate Loop Form, 5.4 Functions and Procedures, 5.4.1 Function and Procedure Parameters, 5.4.2 Overloading, 5.4.3 When to Use Procedures and Functions, 5.4.4 Using Functions and Procedures, 5.5 Attributes, 5.6 Packages, 5.6.1 Organizing and Creating a Library, 5.7 Commonly Used Libraries, 5.71 Simulation Packages, 5.7.2 IEEE_1164, 5.7.3 NUMERIC_STD, 5.7.4 TEXTIO; Appendix: A Quick Reference; A.1 Language Constructs; A.2 Data Types; A.3 Standard Libraries;Index

Details

No. of pages:
200
Language:
English
Copyright:
© Newnes 2011
Published:
Imprint:
Newnes
eBook ISBN:
9780080959399
Paperback ISBN:
9781856177047

About the Author

William Kafig

Affiliations and Expertise

Curriculum Developer, Xilinx Inc., St. Louis, MO, USA