The FPGA Users Guide - 2nd Edition - ISBN: 9780128046371, 9780128047606

The FPGA Users Guide

2nd Edition

Authors: RC Cofer Benjamin Harding
eBook ISBN: 9780128047606
Paperback ISBN: 9780128046371
Imprint: Newnes
Published Date: 1st November 2018
Page Count: 525
Sales tax will be calculated at check-out Price includes VAT/GST

Institutional Access

Secure Checkout

Personal information is secured with SSL technology.

Free Shipping

Free global shipping
No minimum order.

Table of Contents

 CH 1.  Introduction and Lessons Learned

Quick overview of FPGA technology legacy and history;  Continuous technical trend of evolution and innovation; Design skill set crossover (Software and FW skills for HW designers and Hardware skills for Software designers); When FPGAs may be a good fit; When FPGAs may not be a good fit. A lesson learned section will highlight those challenges and mistakes that have historically caused developers issues. Based on these historical accounts, recovery paths and avoidance recommendations when issues arise will be provided.

CH 2.  FPGA Fundamentals and Applications

PLD/CPLD/FPGA device class description overview and evolution; FPGA technologies; Major FPGA Manufacturer overview; High-Level FPGA Resource overview (Common and Specialized). FPGA technology special considerations such as mitigating obsolescence.

 CH 3.  Optimizing the Development Cycle

High-level design flow; Refining and documenting system and performance requirements; Overview of main design phases: System-level architectural design, Capture, Implementation, Simulation, Optimization, Debug, Verification, Support

 CH 4.  System Engineering

Common design challenges and mistakes; Detailed FPGA design process; Project engineering and management; Improving team communication; Effective design reviews – formal and informal; Budgets and scheduling; Training; Design support sources, Design estimation (Schedule, Budget, Performance, Part resources, IO Count, Staff); System architecting; Key design documentation; Tailoring documentation; Design, source and tool configuration management; Tool options and selection; Design capture language options and selection; Key design artifacts; Design archiving

 CH 5.  FPGA Device-level Design Decisions

Manufacturer, Family, Device, Package, Migration Options and Decisions; Key Design decisions, considerations and interaction;                 Data flow orientation at the silicon level (preferred data bus width orientation at the Fabric level); Informed IO assignment (Banks, compatible electrical standards, impedance matching, SSO); Device selection checklist

 CH 6.  Board-Level Design Decisions and Allocation

Packaging, BGA Package considerations; Breakout, board-level rework, BGA to BGA (buried) routing and signal access; Managing iterative IO assignment; FPGA package schematic representation options; Board level thermal calculations and considerations; Device level power supplies; Board layout and component interfaces; Device orientation and placement; Debug access - headers and signal breakout; Configuration cable interface; Signal integrity - Impedance matching, Simultaneous Switching (SSO), signal simulation; Pin signal standard and protocol considerations – differential pairs, drive strength, simultaneous switching, edge rate; Device configuration considerations and options; Power – decoupling, sequencing, sourcing and Isolation

 CH 7.  Design Implementation

Drivers of design architecture; Importance of Synchronous Design; Hierarchical design considerations and implementation; memory interfaces; Team design; Distributed team design; Design entry options and choices; Dual Nature of HDL languages; HDL Coding techniques and guidance; Resources for better HDL coding; Benefits of coding guidelines; Tool suite options and selection; RTL discussion; Design synthesis considerations and options (Logical, Physical); Targeting a design for synthesis; Design Inference vs. Instantiation; IP sources, options, choices and tradeoffs (Reference code, cores, wizards, reuse); Design place and route; Design analysis and reports

 

CH 8.  Design Simulation

Overview simulation options; Simulation tool options, flows and tradeoffs; Evaluating manufacturer vs. 3rd party simulation tool options; How much Simulation is enough?; Hierarchical design and simulation considerations; Common simulation mistakes and tips

 CH 9.  Design Constraints and Optimization

Design constraint overview; Synthesis constraints; Pin constraints; Timing Constraints; Area Constraints; Avoiding design over-constraint; Constraint interaction; Constraint examples; Constraints checklist; Design optimization

 CH 10.  Design Configuration

Board-level device configuration options; Remote configuration;  ; Protecting a "golden" load from corruption; Multiple images and In-the-field design update considerations; Multi-configuration image management and selection; Partial design reconfiguration and considerations; Configuration security; JTAG communication, considerations and checklist

 CH 11.  Board Level Design integration, Debug and Testing

FPGA design validation approaches; Access to critical internal signals; Boundary scan interaction and implementation; Implementation of on-chip "Soft Logic Analyzers"; sufficient resources for on-chip debug; Design debug considerations and checklist

 CH 12.  FPGA Design Life Expectancy Obsolescence

Life-cycle and Obsolescence overview; Options for extending the life cycle of an FPGA based design; Supporting future ability to support and modify a legacy design (operating system, tools, scripts, source, documentation); Design archiving – Not losing the design "recipe"

 CH 13.  (Other Topics: Design Configuration Control, Archiving, Documentation and Deliverables)

What information will you need in the future to support your design?; Reserving sufficient schedule and budget margin to support building a bullet-proof archived design

 

CH 14.  FPGA Design Special Topics

NSEU overview; When, where and how NSEU may be a consideration; NSEU mitigation approaches; DO-254 implementation and considerations; Reducing power consumption; Volume production options; Hardware-co simulation

 CH 15.  Advanced Topics Introduction and Overview

                Transition to Advanced Topics

 CH 16.  Cores and Intellectual Property

Definition of IP; IP Types; IP sources; IP Categories; IP Trade-studies; Make vs. Buy (Leverage and re-use); Source delivery models; IP evaluation options; Qualifying a vendor; Understanding and negotiating custom changes and support; IP Licensing; IP deliverables; ; IP support models; IP implementation flow and tool requirements; IP simulation; IP deliverables & ownership; IP integration; IP testing and debug

 CH 17. Embedded Processing Cores

Embedded processor types (Hard and soft) ; Embedded processor use considerations; System design considerations;  Processor and HW co-design; Processor architecture (buses, co-processors, interfaces, interrupt structures); Tool suite options; Tool Flow considerations; Debug tools and options; Processor implementation; Processor tool version migration; Processor design support; Processor design best practices; Processor core and peripheral selection, interface and integration; Processor bus architecture considerations; Hardware implementation factors; Software implementation factors; Embedded processor implementation design checklist

 CH 18.  Digital Signal Processing

DSP High-level review; DSP Terms; Available DSP resources; Tool options for DSP design implementation; Benefits of parallel processing and  execution;  When implementing a DSP algorithm makes sense to in an FPGA; When it may not make sense to use an FPGA; DSP design considerations; Clocking considerations; Data Flow and signal routing considerations; Pipelining vs. latency; Archiving maximum performance; Power consumption considerations; Resource tradeoff considerations; Hybrid parallel / serial implementation; Algorithm implementation choices and tradeoffs; Available DSP IP; Example Design

 CH 19.  Advanced Interconnect

Interconnection categories; Advanced IO interface challenges and considerations; High Speed IO Serial Interface considerations; Transceiver considerations; Leveraging reference designs

 CH 20.  Bringing It All Together

Example project overview; System-level considerations; Refined requirements; Architectural implementation and hierarchy; Design documentation; Design review implementation; Design capture; Tools and code configuration control and management, Design implementation; Design constraint; Design Simulation; Refining the design; Performance optimization; Design integration; Debug and Testing; Verification and certification; Design prototyping; Effective design archive, Final documentation; Long term support

 

Appendix A - Abbreviations and Acronyms

Appendix B - Design Phases, Milestones, and Gates Checklists

Appendix C - References

Index


Description

The FPGA Users Guide gives both an explanation of the essential technology of FPGAs and practical guidance on implementation, making it highly suitable for engineers, design managers and system engineers. The real-world insight, recommendations and best practices provided will enable design teams to implement a more efficient design flow, leading to earlier product deliveries with optimized performance and extended design life cycles.

Key Features

  • Very experienced, ‘in-the-trenches’, author team
  • End of chapter summaries of key FPGA design skills
  • Checklists on what is needed to be done to be successful

Readership

Professional embedded systems engineers, computer engineering students


Details

No. of pages:
525
Language:
English
Copyright:
© Newnes 2019
Published:
Imprint:
Newnes
eBook ISBN:
9780128047606
Paperback ISBN:
9780128046371

Ratings and Reviews


About the Authors

RC Cofer Author

Affiliations and Expertise

Field Engineer and On-Site Training Specialist, Avnet Corporation, FL, USA

Benjamin Harding Author

Affiliations and Expertise

Field Engineer and On-Site Training Specialist, Avnet Corp., Florida, USA