The Designer's Guide to the Cortex-M Processor Family - 2nd Edition - ISBN: 9780081006290, 9780081006344

The Designer's Guide to the Cortex-M Processor Family

2nd Edition

Authors: Trevor Martin
eBook ISBN: 9780081006344
Paperback ISBN: 9780081006290
Imprint: Newnes
Published Date: 9th June 2016
Page Count: 490
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Description

The Designer’s Guide to the Cortex-M Microcontrollers gives you an easy-to-understand introduction to the concepts required to develop programs in C with a Cortex-M based microcontroller. The book begins with an overview of the Cortex-M family, giving architectural descriptions supported with practical examples, enabling you to easily develop basic C programs to run on the Cortex-M0/M0+/M3 and M4 and M7. It then examines the more advanced features of the Cortex architecture such as memory protection, operating modes, and dual stack operation.

Once a firm grounding in the Cortex-M processor has been established the book introduces the use of a small footprint RTOS and the CMSIS-DSP library. The book also examines techniques for software testing and code reuse specific to Cortex-M microcontrollers. With this book you will learn: the key differences between the Cortex-M0/M0+/M3 and M4 and M7; how to write C programs to run on Cortex-M based processors; how to make the best use of the CoreSight debug system; the Cortex-M operating modes and memory protection; advanced software techniques that can be used on Cortex-M microcontrollers; how to use a Real Time Operating System with Cortex-M devices; how to optimize DSP code for the Cortex-M4; and how to build real time DSP systems.

Key Features

  • Includes an update to the latest version (5) of MDK-ARM, which introduces the concept of using software device packs and software components
  • Includes overviews of the new CMSIS specifications
  • Covers developing software with CMSIS-RTOS showing how to use RTOS in a real world design
  • Provides a new chapter on the Cortex-M7 architecture covering all the new features
  • Includes a new chapter covering test driven development for Cortex-M microcontrollers
  • Features a new chapter on creating software components with CMSIS-Pack and device abstraction with CMSIS-Driver
  • Features a new chapter providing an overview of the ARMv8-M architecture including the TrustZone hardware security model

Readership

Professional embedded systems engineers, software engineers developing embedded systems, students studying embedded systems using ARM technology

Table of Contents

  • Dedication
  • Foreword
  • Preface
  • Acknowledgments
  • Chapter 1. Introduction to the Cortex-M Processor Family
    • Abstract
    • Cortex Profiles
    • Cortex-M3
    • Advanced Architectural Features
    • Cortex-M0
    • Cortex-M0+
    • Cortex-M4
    • DSP Instructions
    • Cortex-M7
    • Conclusion
  • Chapter 2. Developing Software for the Cortex-M Family
    • Abstract
    • Introduction
    • Keil Microcontroller Development Kit
    • Software Packs
    • The Tutorial Exercises
    • Installation
    • Exercise 2.1 Building a First Program
    • The Blinky Project
    • Project Configuration
    • Exercise 2.2 Hardware Debug
    • Conclusion
  • Chapter 3. Cortex-M Architecture
    • Abstract
    • Introduction
    • Cortex-M Instruction Set
    • Programmer’s Model and CPU Registers
    • Program Status Register
    • Q Bit and Saturated Maths Instructions
    • Interrupts and Multicycle Instructions
    • Conditional Execution—If Then Blocks
    • Exercise 3.1 Saturated Maths and Conditional Execution
    • Cortex-M Memory Map and Busses
    • Write Buffer
    • Memory Barrier Instructions
    • System Control Block
    • Bit Manipulation
    • Exercise 3.2 Bit Banding
    • Dedicated Bit Manipulation Instructions
    • SysTick Timer
    • Nested Vector Interrupt Controller
    • Operating Modes
    • Interrupt Handling—Entry
    • Interrupt Handling—Exit
    • Interrupt Handling—Exit Important!
    • Exercise 3.3 SysTick Interrupt
    • Cortex-M Processor Exceptions
    • Priority and Preemption
    • Groups and Subgroup
    • Runtime Priority Control
    • Exception Model
    • Exercise 3.3 Working with Multiple Interrupts
    • Bootloader Support
    • Exercise 3.4 Bootloader
    • Power Management
    • Moving From the Cortex-M3
    • Cortex-M4
    • Cortex-M0
    • Cortex-M0+
    • Conclusion
  • Chapter 4. Cortex Microcontroller Software Interface Standard
    • Abstract
    • Introduction
    • CMSIS Specifications
    • CMSIS-Core
    • CMSIS-RTOS
    • CMSIS-DSP
    • CMSIS-Driver
    • CMSIS-SVD and DAP
    • CMSIS-Pack
    • Foundations of CMSIS
    • Coding Rules
    • MISRA-C
    • CMSIS-Core Structure
    • Startup Code
    • System Code
    • Device Header File
    • CMSIS-Core Header Files
    • Interrupts and Exceptions
    • Exercise 4.1 CMSIS and User Code Comparison
    • CMSIS-Core CPU Intrinsic Instructions
    • Exercise 4.2 Intrinsic Bit Manipulation
    • CMSIS-SIMD Intrinsics
    • CMSIS-Core Debug Functions
    • CMSIS-Core Functions for Corex-M7
    • Conclusion
  • Chapter 5. Advanced Architecture Features
    • Abstract
    • Introduction
    • Cortex Processor Operating Modes
    • Exercise 5.1 Stack Configuration
    • Supervisor Call
    • Exercise 5.2 Supervisor Call
    • PEND_SV Exception
    • Example Pend_SV
    • Interprocessor Events
    • Exclusive Access
    • Exercise 5.4 Exclusive Access
    • Memory Protection Unit
    • Configuring the MPU
    • Exercise 5.5 MPU Configuration
    • MPU Subregions
    • MPU Limitations
    • AHB Lite Bus Interface
    • Conclusion
  • Chapter 6. Cortex-M7 Processor
    • Abstract
    • Superscalar Architecture
    • Branch Prediction
    • Exercise 6.1 Simple Loop
    • Bus Structure
    • Memory Hierarchy
    • Exercise 6.2 Locating Code and Data into the TCM
    • Cache Units
    • Cache Operation
    • Instruction Cache
    • Exercise 6.3 Instruction Cache
    • Data Cache
    • Memory Barriers
    • Exercise 6.4 Example Data Cache
    • Memory Protection Unit and Cache Configuration
    • Cache Policy
    • Managing the Data Cache
    • Exercise 6.5 Data Cache Configuration
    • Double Precision Floating Point Unit
    • Functional Safety
    • Cortex-M7 Safety Features
    • Safety Documentation
    • Development Tools
    • Conclusion
  • Chapter 7. Debugging with CoreSight
    • Abstract
    • Introduction
    • CoreSight Hardware
    • Debugger Hardware
    • CoreSight Debug Architecture
    • Exercise 7.1 CoreSight Debug
    • Hardware Configuration
    • Software Configuration
    • Debug Limitations
    • Instrumentation Trace
    • Exercise 7.2 Setting Up the ITM
    • System Control Block Debug Support
    • Tracking Faults
    • Exercise 7.3 Processor Fault Exceptions
    • Instruction Trace with the Embedded Trace Macrocell
    • Exercise 7.4 Using the ETM Trace
    • CMSIS-DAP
    • Cortex-M0+ MTB
    • Exercise 7.5 Micro Trace Buffer
    • CMSIS System Viewer Description
    • Exercise 7.6 CMSIS-SVD
    • Conclusion Debug Features Summary
  • Chapter 8. Practical DSP for Cortex-M4 and Cortex-M7
    • Abstract
    • Introduction
    • Hardware FPU
    • FPU Integration
    • FPU Registers
    • Cortex-M7 FPU
    • Enabling the FPU
    • Exceptions and the FPU
    • Using the FPU
    • Exercise 8.1 Floating Point Unit
    • Cortex-M4/M7 DSP and SIMD Instructions
    • Exercise 8.2 SIMD Instructions
    • Exercise 8.3 Optimizing DSP Algorithms
    • The CMSIS-DSP Library
    • CMSIS-DSP Library Functions
    • Exercise 8.3 Using the CMSIS-DSP Library
    • DSP Data Processing Techniques
    • Exercise 8.4 FIR Filter with Block Processing
    • Fixed Point DSP with Q Numbers
    • Exercise 8.5 Fixed Point FFT Transform
    • Conclusion
  • Chapter 9. Cortex Microcontroller Software Interface Standard-Real-Time Operating System
    • Abstract
    • Introduction
    • First Steps with CMSIS-RTOS
    • Accessing the CMSIS-RTOS API
    • Threads
    • Starting the RTOS
    • Exercise 9.1 A First CMSIS-RTOS Project
    • Creating Threads
    • Exercise 9.2 Creating and Managing Threads
    • Thread Management and Priority
    • Exercise 9.3 Creating and Managing Threads II
    • Multiple Instances
    • Exercise 9.4 Multiple Thread Instances
    • Time Management
    • Time Delay
    • Waiting for an Event
    • Exercise 9.5 Time Management
    • Virtual Timers
    • Exercise 9.6 Virtual Timer
    • Sub-Millisecond Delays
    • Idle Demon
    • Exercise 9.7 Idle Thread
    • Inter-Thread Communication
    • Signals
    • Exercise 9.8 Signals
    • Semaphores
    • Exercise 9.9 Semaphore Signaling
    • Using Semaphores
    • Signaling
    • Multiplex
    • Exercise 9.10 Multiplex
    • Rendezvous
    • Exercise 9.11 Rendezvous
    • Barrier Turnstile
    • Exercise 9.12 Semaphore Barrier
    • Semaphore Caveats
    • Mutex
    • Exercise 9.13 Mutex
    • Mutex Caveats
    • Data Exchange
    • Message Queue
    • Exercise 9.14 Message Queue
    • Memory Pool
    • Exercise 9.15 Memory Pool
    • Mail Queue
    • Exercise 9.16 Mailbox
    • Configuration
    • Thread Definition
    • Kernel Debug Support
    • System Timer Configuration
    • Timeslice Configuration
    • Scheduling Options
    • RTX Source Code
    • RTX License
    • Conclusion
  • Chapter 10. RTOS Techniques
    • Abstract
    • Introduction
    • RTOS and Interrupts
    • RTOS Interrupt Handling
    • Exercise 10.1 RTOS Interrupt Exercise Handling
    • User Supervisor Functions
    • Exercise 10.2 RTOS and User SVC Exceptions
    • Power Management
    • Power Management First Steps
    • Power Management Strategy
    • Watchdog Management
    • Integrating ISRs
    • Exercise 10.3 Power and Watchdog Management
    • Startup Barrier
    • Designing for Real Time
    • Exercise 10.4 RTX Real Time
    • Shouldering the Load, the Direct Memory Access Controller
    • Designing for Debug
    • Exercise 10.5 Run-Time Diagnostics
    • Conclusion
  • Chapter 11. Test Driven Development
    • Abstract
    • Introduction
    • Installing the Unity Framework
    • Exercise 11.1 Test Driven Development
    • Testing RTOS Threads
    • Exercise 11.2 Testing RTOS Threads
    • Exercise 11.3 Testing with Interrupts
    • Conclusion
  • Chapter 12. Software Components
    • Abstract
    • Introduction
    • CMSIS Driver
    • Driver Validation
    • Designing a Software Component
    • Creating a Software Pack
    • Configuration Wizard
    • Deploying Software Components
    • Conclusion
  • Chapter 13. ARMv8-M
    • Abstract
    • Introduction
    • Common Architectural Enhancements
    • ARMv8 Baseline Enhancements
    • ARMv8-M Mainline Enhancements
    • TrustZone
    • Software Development
    • Conclusion
  • Appendix
    • Contact Details
    • Appendices
    • Debug Tools and Software
    • Real-Time Operating Systems
    • Books
    • Cortex-M Processor
    • Standards
    • Digital Signal Processing
    • Real-Time Operating System
    • Silicon Vendors
    • Training
  • Index

Details

No. of pages:
490
Language:
English
Copyright:
© Newnes 2016
Published:
Imprint:
Newnes
eBook ISBN:
9780081006344
Paperback ISBN:
9780081006290

About the Author

Trevor Martin

Trevor Martin graduated from Brunel University in 1988 with an Honors degree in Electrical and Electronic Engineering. In the same year he began work as a Junior Hardware engineer at Philips Medical Systems. He joined Hitex in 1992 as a Technical specialist for 8 Bit Microcontroller development tools. This included the 8051,68HC11\05\08 microcontrollers. He also gained experience with networking protocols such as CAN,USB and TCP/IP. Since 2000 he has been supporting ARM based microcontrollers, initially ARM7 and ARM9 CPU then moving to Cortex-M processor. To promote these devices he has worked closely with both NXP and ST and also TI and Freescale to a lesser extent. Since 2005 he has written a number of „Insiders Guide‟ Books which are introductory tutorials to ARM based microcontroller families such as LPC2000, STR9 and STM32. He also runs regular training courses, a general Cortex Microcontroller workshop and also device specific courses.

Affiliations and Expertise

Technical Specialist, Hitex (UK) Ltd.