System-on-Chip Test Architectures
Nanometer Design for Testability
Free Global Shipping
No minimum orderDescription
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Key Features
- Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
- Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
- Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
- Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
- Practical problems at the end of each chapter for students.
Readership
Practitioners/Researchers in VLSI Design and Testing; Design or Test Engineers, as well as research institutes.
Table of Contents
- Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
Product details
- No. of pages: 896
- Language: English
- Copyright: © Morgan Kaufmann 2007
- Published: November 20, 2007
- Imprint: Morgan Kaufmann
- eBook ISBN: 9780080556802
- Hardcover ISBN: 9780123739735
About the Authors
Laung-Terng Wang
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).
Affiliations and Expertise
SynTest Technologies, Inc., Sunnyvale, CA, USA
Charles Stroud
Affiliations and Expertise
Auburn University, Auburn, AL, U.S.A.
Nur Touba
Affiliations and Expertise
University of Texas, Austin, TX, U.S.A.
Ratings and Reviews
There are currently no reviews for "System-on-Chip Test Architectures"