System on Chip Interfaces for Low Power Design
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System on Chip Interfaces for Low Power Design provides a top-down understanding of interfaces available to SoC developers, not only the underlying protocols and architecture of each, but also how they interact and the tradeoffs involved. The book offers a common context to help understand the variety of available interfaces and make sense of technology from different vendors aligned with multiple standards. With particular emphasis on power as a factor, the authors explain how each interface performs in various usage scenarios and discuss their advantages and disadvantages. Readers learn to make educated decisions on what interfaces to use when designing systems and gain insight for innovating new/custom interfaces for a subsystem and their potential impact.
Key Features
- Provides a top-down guide to SoC interfaces for memory, multimedia, sensors, display, and communication
- Explores the underlying protocols and architecture of each interface with multiple examples
- Guides through competing standards and explains how different interfaces might interact or interfere with each other
- Explains challenges in system design, validation, debugging and their impact on development
Readership
Software/hardware engineers, system architects, technical program and product managers involved in architecting, designing, developing, validating, reviewing and deploying systems based on SoC, as well as graduate students studying this field.
Table of Contents
- Dedication
- Acknowledgments
- Chapter 1: SoC Design Fundamentals and Evolution
- Abstract
- Introduction
- System Approach to Design
- Hardware IC Design Fundamentals
- Chip Design Tradeoff
- Chapter 2: Understanding Power Consumption Fundamentals
- Abstract
- Why Power Optimization is Important
- Power Consumption of a System
- Chapter 3: Generic SoC Architecture Components
- Abstract
- Generic SoC Block Diagram
- Subsystems of an SoC
- Conclusion
- Chapter 4: Display Interfaces
- Abstract
- Generic Display Concepts
- Display Interface Overview
- Display Interface Classification
- External Display Interface
- Internal Display Interface
- 3D Displays
- Conclusion
- Chapter 5: Multimedia Interfaces
- Abstract
- Introduction
- I2C Bus
- Audio
- Graphics Components and Their Significance in the SoC
- Imaging Subsystem
- Chapter 6: Communication Interfaces
- Abstract
- Bluetooth Interfaces
- Wi-Fi Interfaces
- 2G/3G/4G Interfaces
- GPS Interfaces
- NFC Interfaces
- Summary
- Chapter 7: Memory Interfaces
- Abstract
- Volatile Memory Interface
- Nonvolatile Memory Interface
- Conclusion
- Chapter 8: Security Interfaces
- Abstract
- Near Field Communication
- Trusted Platform Module
- Smart Card
- Summary
- Chapter 9: Power Interfaces
- Abstract
- Voltage Regulation
- Battery Charging
- Summary
- Chapter 10: Sensor Interfaces
- Abstract
- Inter-Integrated Circuit
- Serial Peripheral Interface (SPI)
- Universal Asynchronous Receiver Transmitter (UART)
- Universal Serial Bus (USB)
- Summary
- Chapter 11: Input Device Interfaces
- Abstract
- Keyboard
- Mouse
- Remote Control
- Summary
- Chapter 12: Debug Interfaces
- Abstract
- Debugger Setup and Operation
- UART
- USB
- Joint Test Action Group
- Nexus
- Appendix A: Overview of Intel SoC: Baytrail
- Baytrail Reference Validation Platform Block Diagram
- Appendix B: Industry Consortiums
- Appendix C: USB 3.0
- Motivation for USB 3.0
- Protocol Overview
- Summary
- Appendix D: USB OTG (On The Go)
- Motivation and protocol overview of USB OTG
- References
- Index
Product details
- No. of pages: 406
- Language: English
- Copyright: © Morgan Kaufmann 2015
- Published: November 17, 2015
- Imprint: Morgan Kaufmann
- Paperback ISBN: 9780128016305
- eBook ISBN: 9780128017906
About the Authors
Sanjeeb Mishra
Sanjeeb Mishra is a Validation Architect with Intel. He has 15 years of experience ranging from hardware system design to SOC validation for telecom, consumer electronics, PC and mobility products; and has specific expertise on SoC architecture for mobile devices.
Affiliations and Expertise
Validation Architect, Mobile Communications Group - Tablet Product Development, Intel.
Neeraj Kumar Singh
Neeraj Kumar Singh is a Platform Architect for tablet platforms at Intel. Prior to this he worked on CPU, Graphics and Chipset validation tools. His areas of expertise are hardware software co-design, SoC system architecture, and system software design and development.
Affiliations and Expertise
Platform Architect for tablet platforms at Intel
Vijayakrishnan Rousseau
Vijayakrishnan Rousseau is a Technical Lead at Intel. He has 15 years of experience in GPU and SOC validation with specialization in Display interfaces like HDMI, Display Port and Emulation.
Affiliations and Expertise
Technical Lead, Visual and Parallel Computing Group, Intel
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