Description

Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI.

Key Features

  • Comprehensive guide to precharge logic
  • Explains both the advantages and disadvantages to help engineers decide when to utilize precharge logic
  • Useful for engineers in a variety of industries

Readership

Professional engineers and students learning about processor and logic design.

Table of Contents

  • Dedication
  • List of figures
  • List of tables
  • About the author
  • 1. Precharge Logic Basics
    • 1.1 Introduction
    • 1.2 What Is Precharge Logic?
    • 1.3 Why Is it Faster than Static Logic?
    • 1.4 Advantages of Precharge Logic
    • 1.5 What About Using Other Transistors?
    • 1.6 Domino Logic
    • 1.7 Keepers: Improving the Charge Storage
    • 1.8 Final Comments
  • 2. Timing
    • 2.1 Clock Skew Penalty
    • 2.2 Hold-Time Problem
    • 2.3 Nonoverlapping Clocks
    • 2.4 A Better Latch
    • 2.5 Input Setup Criteria
    • 2.6 Input Hold Criteria
    • 2.7 Precharge Timing
    • 2.8 Skew Tolerant Design
  • 3. Transistor Sizing
    • 3.1 Sizing the Pulldown Stack
    • 3.2 Sizing of the Output Inverter
    • 3.3 Logical Effort
    • 3.4 Sizing of the Keeper Device
    • 3.5 Sizing of the Precharge Device
    • 3.6 Sizing Precharge Gates with Wires
  • 4. Noise Tolerance
    • 4.1 Input-Connected Prechargers
    • 4.2 Propagated Noise
    • 4.3 Input Wire Noise
    • 4.4 Supply-Level Variations
    • 4.5 Charge Sharing
    • 4.6 Charge Sharing: Example 1
    • 4.7 Charge Sharing: Example 2
    • 4.8 Leakage
    • 4.9 Clock Coupling on the Internal Dynamic Node
    • 4.10 Minority Carrier Charge Injection
    • 4.11 Alpha Particles
    • 4.12 Noise Induced on Dynamic Nodes Directly
    • 4.13 Example of Transistor Crosstalk During Precharge
    • 4.14 CSR Latch Signal Ordering
    • 4.15 Interfacing to Transmission Gates
  • 5. Topology Considerations
    • 5.1 Limitation on Device Stacking
    • 5.2 Limitation of Logic Width
    • 5.3 Use of Low/High Vt Transistors
    • 5.4 Sharing Evaluation Devices
    • 5.5 Tapering of the Evaluation Device
    • 5.6 Footed versus U

Details

No. of pages:
112
Language:
English
Copyright:
© 2012
Published:
Imprint:
Elsevier
Print ISBN:
9780123985279
Electronic ISBN:
9780124017078

About the author

Marek Smoszna

Marek Smoszna is a memory design engineer at NVIDIA Corporation. He was born in Poland in 1972. He received his BS and MS in electrical engineering from Rensselaer Polytechnic Institute in 1995 and 1996, respectively. He holds two patents in the area of memory design with several other patent applications filed. His interests include high speed circuit and memory design. When not doing circuit design he can be found with his children at the beach.