Sustainable Wireless Network-on-Chip Architectures

Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed—combined with extensive experimental validation—collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern.

The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots.

• Defines new complex, sustainable network-on-chip architectures to reduce network latency and energy
• Develops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniques
• Describes joint strategies for network- and core-level sustainability
• Discusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures

Graduate level research interest. Professionals performing research corresponding to sustainable computing or networks-on-chip would find interest in this material. Senior-level undergraduate or graduate student technical elective courses; the topics described in this book would be applicable to advanced courses in VLSI.

• Chapter 1. Introduction
  • Abstract
  • The Network-on-Chip Paradigm
  • Traditional NoC Interconnect Topologies
  • Traditional NoC Routing
  • Traditional NoC Backbone
  • References
• Chapter 2. Current Research Trends and State-of-the-Art NoC Designs
  • Abstract
  • The Small-World Topology (and Other Irregular Topologies)
  • Design for Topology-Agnostic Routing for Irregular Networks
  • 3D, Optical, and Wireless Integration for NoC
  • Power- and Temperature-Aware Design Considerations
  • References
• Chapter 3. Complex Network Inspired NoC Architecture
  • Abstract
  • Distance Between Cores (lij)
  • Frequency of Interaction Between Cores (fij)
  • Alpha and Beta
  • fij for Various Traffic Patterns
  • The Small-World Characteristic
  • References
  • Appendix A.1 Lij matrix for a 16 core NoC with a tile floorplan
  • Appendix A.2 Fij matrix for uniform random traffic
  • Appendix A.3 Fij matrix for transpose traffic
  • Appendix A.4 Fij matrix for hotspot traffic
• Chapter 4. Wireless Small-World NoCs
  • Abstract
  • Wireless Physical Layer Design
  • Communication and Channelization
  • Topology of Wireless NoCs
  • References
• Chapter 5. Topology-Agnostic Routing for Irregular Networks
  • Abstract
  • A Simple Approach to Topology-Agnostic Routing
  • Routing Strategy for Hierarchical Wireless Small-World Networks
  • Advanced Routing Strategies for Wireless Small-World Networks
  • References
• Chapter 6. Performance Evaluation and Design Trade-Offs of Wireless SWNoCs
  • Abstract
  • Performance Metrics
  • Optimal Configuration of the SWNoC
  • Throughput of CSWNoC
  • Energy Dissipation for CSWNoC
  • Packet Latency and Energy Dissipation of mSWNoC
  • References
• Chapter 7. Dynamic Voltage and Frequency Scaling
  • Abstract
  • Processor-Level DVFS
  • Network-Level DVFS
  • Performance Evaluation
  • References
• Chapter 8. Dynamic Thermal Management
  • Abstract
  • Temperature-Aware Task Allocation
  • Temperature-Aware Adaptive Routing
  • Experimental Results
  • References
• Chapter 9. Joint DTM and DVFS Techniques
  • Abstract
  • Enhanced Routing and Dynamic Thermal Management
  • Joint DTM/DVFS
  • Experimental Results
  • References
• Chapter 10. Conclusions and Possible Future Explorations
  • Abstract
  • Design of 3D Wireless Small-World NoCs
  • DVFS Pruning
  • Voltage Frequency Island
  • Concluding Remarks
  • References