RISC System/6000 PowerPC System Architecture - 1st Edition - ISBN: 9781558603448, 9780080516318

RISC System/6000 PowerPC System Architecture

1st Edition

Hardcover ISBN: 9781558603448
eBook ISBN: 9780080516318
Imprint: Morgan Kaufmann
Page Count: 320
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Offers support for a wide range of products for the RISC System/6000 product line and AIX operating system, including Uni-processor (UP) and Symmetric Multiple Processor (SMP) systems. Provides important information for building many system features such as memory controllers with caches and bus-to-bus bridges. RISC System/ 6000 PowerPC System Architecture defines an architecture that allows each operating system--in particular, the AIX operating system--to run unchanged on all systems that comply with this architecture. It provides a consistent software interface across a broad range of system implementations and offers all hardware/software dependencies necessary for a successful system identification, configuration and performance tuning process.

An important reference for all programmers and product development engineers who are developing software and hardware products for the RISC/System 6000 PowerPC systems. Also useful for system programmers involved in operating system design, system integrators building products and parts for the system family, and anyone interested in porting other operating systems to the RISC System/6000 family.

Table of Contents

RISC System/6000: PowerPC System Architecture
by International Business Machines, Inc.

    List of Figures
    List of Tables
    Chapter 1 Introduction

      1.1 Memory Architecture
      1.2 Definition of Terms

        1.2.1 Reserved
        1.2.2 Reserved/Unimplemented
        1.2.3 Addressing Notation
        1.2.4 Symbolic Notation
      1.3 Reliability, Availability, and Serviceability (RAS)

    Chapter 2 PowerPC Processor Architecture

      2.1 PowerPC Implementation Specific User's Manual

        2.1.1 Processor Requirements
        2.1.2 Hardware I/O Design Instruction Support Requirements

    Chapter 3 Architected system Memory Map

      3.1 Memory Map Layout
      3.2 Architected System Registers

        3.2.1 Physical Identifier Initialization (PIDI) Register
        3.2.2 Connectivity Configuration Register
        3.2.3 Connectivity Reset Register
        3.2.4 time of Day Registers
        3.2.5 System Reset count Register
        3.2.6 Power/Keylock Status Register (PKSR)
        3.2.7 Software Power on Reset Control Register
        3.2.8 Software Power Off Control Register
        3.2.9 System Specific System Registers
      3.3 Architected System Interrupt Registers

        3.3.1 Data Storage Interrupt Error Register (DSIER)
        3.3.2 SMP Early Power Off Warning (EPOW) External Interrupt Vector Register (XIVR)
        3.3.3 IPLCB/Global Queue Interrupt Routing Mask Location Interface



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© Morgan Kaufmann 1994
Morgan Kaufmann
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