Resource Efficient LDPC Decoders - 1st Edition - ISBN: 9780128112557

Resource Efficient LDPC Decoders

1st Edition

From Algorithms to Hardware Architectures

Authors: Vikram Chandrasetty
Paperback ISBN: 9780128112557
Imprint: Academic Press
Published Date: 15th December 2017
Page Count: 192
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This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.
The reader will learn:

  • Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation
  • How to reduce computational complexity and power consumption using computer aided design techniques
  • All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs

Key Features

    • Provides extensive treatment of LDPC decoding algorithms and hardware implementations
    • Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware
    • Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis


    Electrical and electronic engineers in academia and industry involved in the design of communication circuits; Research and development engineers in various government research organizations. Postgraduate research students (PhD and Masters) engaged in research in telecommunications and electronic engineering

    Table of Contents

    1.1. Error correction in digital communication
    1.2. Forward error correction codes
    2. Overview of LDPC codes
    2.1. Origin of LDPC codes
    2.2. Types of LDPC codes
    2.2.1. Regular and irregular codes
    2.2.2. Random and pseudo-random codes
    2.2.3. Structured and unstructured codes
    2.3. Terminologies in LDPC codes
    2.3.1. LDPC code parameters
    2.3.2. Simulation parameters
    2.3.3. Performance metrics
    2.4. Summary
    3. Structure and flexibility of LDPC codes
    3.1. Common construction techniques
    3.1.1. Progressive edge growth algorithm
    3.1.2. Quasi-cyclic algorithm
    3.1.3. Spatially-coupled codes
    3.1.4. Repeat-accumulate codes
    3.2. Flexible matrices
    3.2.1. Structure of the matrix
    3.2.2. Construction technique
    3.2.3. Standard matrix configurations
    3.2.4. Visual analysis
    3.2.5. Performance analysis
    3.3. Summary
    4. LDPC decoding algorithms
    4.1. Standard decoding algorithms
    4.1.1. Bit-Flip algorithm
    4.1.2. Sum-Product algorithm
    4.1.3. Min-Sum algorithm
    4.1.4. Stochastic algorithm
    4.2. Reduced complexity algorithms
    4.2.1. Simplified message passing
    4.2.2. Modified Min-Sum
    4.3. Performance analysis of simplified algorithms
    4.3.1.Extraction of optimized parameters
    4.3.2.Performance comparison
    5. LDPC decoder architectures
    5.1. Most common hardware architectures
    5.1.1. Fully- parallel
    5.1.2. Fully-serial
    5.1.3. Partially-parallel
    5.2. Literature review of LDPC decoders
    5.3. Summary
    6. Hardware implementation of LDPC decoder
    6.1. Decoder design methodology
    6.1.1. Design and implementation
    6.1.2. Performance measurement
    6.2. Prototyping LDPC codes in hardware
    6.3. Implementation of hardware efficient decoder
    6.3.1. Fully-parallel architecture
    6.3.2. Partially-parallel architecture
    6.3.3. Performance analysis
    6.4. Design space exploration
    6.4.1. Decoding performance
    6.4.2. Hardware performance
    6.5. Summary
    7. LDPC decoders in multimedia communication
    7.1. Image communication using LDPC codes
    7.2. Performance analysis
    7.2.1. Quality of the reconstructed BMP images
    7.2.2. Quality of the reconstructed JPEG images
    7.2.3. Reconstructed JPEG images for various decoders
    7.3. Summary
    8. Prospective LDPC applications
    8.1. Wireless communication
    8.2. Optical communication
    8.3. Flash memory devices
    Appendix-A : Sample C-Programs and MATLAB models for LDPC code construction and simulation
    Appendix-B : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architecture
    Appendix-C : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture


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    © Academic Press 2018
    Academic Press
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    About the Author

    Vikram Chandrasetty

    Vikram Chandrasetty received Bachelor Degree in Electronics and Communication Engineering from Bangalore University (INDIA), Master Degree in VLSI System Design from Coventry University (UK) and PhD in Computer Systems Engineering from the University of South Australia (Australia). During his post-doctoral research fellowship at the University of New Castle (Australia) he worked on designing spatially coupled LDPC codes and hardware implementations. He reviews articles for many journals including Elsevier and IEEE Transactions. Vikram also has substantial experience as a professional engineer. He has worked on ASIC/FPGA design, error correction coding, electronic design automation, cryptography and communication systems for renowned companies including Motorola and SanDisk. He is currently working on designing memory controllers for next generation storage products in Western Digital.

    Affiliations and Expertise

    Principal Engineer, ASIC Design, Western Digital Corporation