Plasma Etching Processes for Interconnect Realization in VLSI

This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions.

This book focuses on back end of line (BEOL) for high performance device realization and presents an overview of all etch challenges for interconnect realization as well as the current etch solutions proposed in the semiconductor industry. The choice of copper/low-k interconnect architecture is one of the keys for integrated circuit performance, process manufacturability and scalability.

Today, implementation of porous low-k material is mandatory in order to minimize signal propagation delay in interconnections. In this context, the traditional plasma process issues (plasma-induced damage, dimension and profile control, selectivity) and new emerging challenges (residue formation, dielectric wiggling) are critical points of research in order to control the reliability and reduce defects in interconnects. These issues and potential solutions are illustrated by the authors through different process architectures available in the semiconductor industry (metallic or organic hard mask strategies).

• Presents the difficulties encountered for interconnect realization in very large-scale integrated (VLSI) circuits
• Focused on plasma-dielectric surface interaction
• Helps you further reduce the dielectric constant for the future technological nodes

Academics, students and researchers studying electronics and information systems and nanotechnology; researchers and engineers within the microelectronics industry

<li>List of Acronyms</li> <li>Preface</li> <li>1. Introduction<ul><li>Abstract</li><li>1.1 Integration processes related to copper introduction</li><li>1.2 Dielectric material with low-<i>k</i> value (&lt;4)</li></ul></li> <li>2. Interaction Plasma/Dielectric<ul><li>Abstract</li><li>2.1 Porous SiOCH film etching</li><li>2.2 Porous SiOCH film sensitivity to post-etch treatments</li></ul></li> <li>3. Porous SiOCH Film Integration<ul><li>Abstract</li><li>3.1 Trench first metallic hard mask integration</li><li>3.2 Porous SiOCH integration using the via first approach</li><li>3.3 Summary</li></ul></li> <li>4. Interconnects for Tomorrow<ul><li>Abstract</li><li>4.1 Consequence of porosity increase</li><li>4.2 Process solutions for dielectric constant reduction</li><li>4.3 Material solutions for dielectric constant reduction</li><li>4.4 Alternative interconnect architectures for dielectric constant reduction</li><li>4.5 Conclusion</li></ul></li> <li>Bibliography</li> <li>List of Authors</li> <li>Index</li>