Plasma Etching Processes for CMOS Devices Realization

Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent.
Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography.
This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization.

• Helps readers discover the master technology used to pattern complex structures involving various materials
• Explores the capabilities of cold plasmas to generate well controlled etched profiles and high etch selectivities between materials
• Teaches users how etch compensation helps to create devices that are smaller than 20 nm

Postgraduate students, academics, and researchers of materials science and materials engineers within the semiconductor industry

1: CMOS Devices Through the Years

Abstract

1.1 Scaling law by Dennard

1.2 CMOS device improvement through the years

1.3 Summary

1.4 What is coming next?

2: Plasma Etching in Microelectronics

Abstract

2.1 Overview of plasmas and plasma etch tools

2.2 Plasma surface interactions during plasma etching

2.3 Patterns transfer by plasma etching

2.4 Conclusion

3: Patterning Challenges in Microelectronics

Abstract

3.1 Optical immersion lithography

3.2 Next-generation lithography

3.3 Conclusion

4: Plasma Etch Challenges for Gate Patterning

Abstract

4.1 pSi gate etching

4.2 Metal gate etching

4.3 Stopping on the gate oxide

4.4 High-k dielectric etching

4.5 Line width roughness transfer during gate patterning

4.6 Chamber wall consideration after gate patterning

4.7 Summary