
Plasma Etching Processes for CMOS Devices Realization
Description
Key Features
- Helps readers discover the master technology used to pattern complex structures involving various materials
- Explores the capabilities of cold plasmas to generate well controlled etched profiles and high etch selectivities between materials
- Teaches users how etch compensation helps to create devices that are smaller than 20 nm
Readership
Table of Contents
1: CMOS Devices Through the Years
Abstract
1.1 Scaling law by Dennard
1.2 CMOS device improvement through the years
1.3 Summary
1.4 What is coming next?
2: Plasma Etching in Microelectronics
Abstract
2.1 Overview of plasmas and plasma etch tools
2.2 Plasma surface interactions during plasma etching
2.3 Patterns transfer by plasma etching
2.4 Conclusion
3: Patterning Challenges in Microelectronics
Abstract
3.1 Optical immersion lithography
3.2 Next-generation lithography
3.3 Conclusion
4: Plasma Etch Challenges for Gate Patterning
Abstract
4.1 pSi gate etching
4.2 Metal gate etching
4.3 Stopping on the gate oxide
4.4 High-k dielectric etching
4.5 Line width roughness transfer during gate patterning
4.6 Chamber wall consideration after gate patterning
4.7 Summary
Product details
- No. of pages: 136
- Language: English
- Copyright: © ISTE Press - Elsevier 2017
- Published: January 18, 2017
- Imprint: ISTE Press - Elsevier
- eBook ISBN: 9780081011966
- Hardcover ISBN: 9781785480966
About the Editor
Nicolas Posseme
Affiliations and Expertise
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