Open Radio Access Network (O-RAN) Systems Architecture and Design

Open Radio Access Network (O-RAN) Systems Architecture and Design

1st Edition - February 26, 2022

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  • Author: Wim Rouwet
  • eBook ISBN: 9780323919227
  • Paperback ISBN: 9780323919234

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Open Radio Access Network (O-RAN) Systems Architecture and Design gives a jump-start to engineers developing O-RAN hardware and software systems, providing a top-down approach to O-RAN systems design. It gives an introduction into why wireless systems look the way they do today before introducing relevant O-RAN and 3GPP standards. The remainder of the book discusses hardware and software aspects of O-RAN system design, including dimensioning and performance targets.

Key Features

  • Presents O-RAN and 3GPP standards
  • Provides a top-down approach to O-RAN systems design
  • Includes practical examples of relevant elements of detailed hardware and software design to provide tools for development
  • Gives a few practical examples of where O-RAN designs play in the market and how they map to hardware and software architectures


Hardware and software engineers as well as product managers and consumers of O-RAN products looking to understand O-RAN

Table of Contents

  • Cover image
  • Title page
  • Table of Contents
  • Copyright
  • About the authors
  • Preface
  • Acronyms
  • 1. Open radio access network overview
  • Abstract
  • The Open Radio Access Networks Alliance
  • On C-RAN, Open vRAN, OpenRAN, xRAN, and Telecommunications Infrastructure Project
  • Spectrum: enabling 5G
  • Traditional base station architectures
  • 5G base station architectures
  • Functional splits
  • Coordinated Multipoint
  • A real-life example: enterprise 5G networking
  • Summary and conclusions
  • References
  • Further reading
  • 2. System components, requirements, and interfaces
  • Abstract
  • Next-Generation Radio Access Network overview and terminology
  • Central unit
  • Distributed unit
  • Radio unit
  • Distributed unit/radio unit interface, Enhanced Common Public Radio Interface protocol overview
  • Initial access
  • 802.1CM
  • Fronthaul gateway
  • Cell site router/gateway
  • Form factor, environmental and power requirements
  • ASN.1
  • DiffServ
  • References
  • 3. Hardware system dimensioning
  • Abstract
  • Centralized/distributed unit use-case dimensioning for throughput
  • Use-case dimensioning for latency
  • Users/transmission time interval
  • eCPRI, fronthaul bandwidth and latency
  • Distributed unit internal IO
  • Memory dimensioning
  • HARQ process count dimensioning
  • Radio unit
  • References
  • Further reading
  • 4. Hardware architecture choices
  • Abstract
  • Scalability
  • Development cycle
  • Data center architecture
  • Cell site integrated (CU/DU) solutions
  • Radio unit
  • Integrated small cell
  • Multicore central processing unit selection criteria
  • PCIe performance
  • References
  • 5. System software
  • Abstract
  • Operating system
  • Networking stacks
  • Functional application platform interface
  • Security aspects
  • References
  • Further reading
  • 6. User-plane application components
  • Abstract
  • GTP Protocol
  • PDCP protocol
  • RLC Protocol
  • MAC protocol
  • eCPRI protocol overview
  • Low physical layer
  • Digital front-end
  • References
  • Further reading
  • 7. Wireless scheduling and Quality of Service optimization techniques
  • Abstract
  • Orthogonal frequency division multiple access
  • Base station scheduler algorithms
  • Architectural framework for the base station wireless scheduler algorithm
  • System-level optimization
  • Software optimization techniques
  • References
  • Further reading
  • 8. Synchronization in open radio access networks
  • Abstract
  • Understanding frequency, time, syntonization, and synchronization
  • How do we get time?
  • O-RAN synchronization
  • Cellular network synchronization requirements
  • Synchronization in O-RAN
  • O-RAN network-level synchronization
  • O-RAN sync equipment requirements
  • Sync solution implementation
  • The effects of timestamping location and resolution
  • Unraveling the standards spaghetti
  • Further reading
  • 9. Software performance
  • Abstract
  • Packet processing cycle budget analysis
  • Physical Layer complexity analysis
  • Central Processing Unit loading summary
  • System-on-Chip performance counters
  • Life-of-a-packet double data rate utilization analysis
  • Mitigation techniques: what if the product does not meet performance targets?
  • Development environment optimization
  • Software optimization techniques
  • Reference
  • 10. Interoperability and test
  • Abstract
  • Development testing
  • System test setup
  • Performance testing
  • Front-, mid-, and backhaul testing
  • Operator acceptance testing
  • Regulatory approval testing
  • References
  • 11. Differentiation by use case
  • Abstract
  • Ultra-reliable low-latency communication
  • Vehicle-to-infrastructure (vehicle-to-anything) roadside unit architecture and implementation
  • 5G Reduced Capabilities (RedCap)
  • References
  • Further reading
  • Index

Product details

  • No. of pages: 402
  • Language: English
  • Copyright: © Academic Press 2022
  • Published: February 26, 2022
  • Imprint: Academic Press
  • eBook ISBN: 9780323919227
  • Paperback ISBN: 9780323919234

About the Author

Wim Rouwet

Wim Rouwet is a Distinguished Member of Technical Staff at NXP. He has a MSc in Electrical Engineering from Eindhoven University of Technology in the Netherlands. He spent 15+ years in Motorola, Freescale and NXP in networking and network processing, wireless algorithm development, system and modem architecture. His focus is on 3GPP LTE and 5G as well as 802.11 processing stacks and their implementation. In this role, he has been responsible for 4G and 5G stack development, small cells, and CRAN implementations associated with many wireless infrastructure projects. He has lead key next generation R&D projects including multi-standard modem architecture, virtualization and 5G small cell as well as CPE products.

Affiliations and Expertise

Distinguished Member of Technical Staff at NXP, USA

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