The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution.
This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.
- Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends
- An integrated presentation not currently available in any other book
- A thorough introduction to current design methodologies and chips designed with NoCs
Primary: Researchers/Practitioners in Multiprocessor Systems on Chips; Networks on Chips. VLSI design companies (ST Microelectronics, Arteris, etc.) involved currently with implementing NoCs on silicon.
Secondary: Graduate-level courses in System on Chip design.
I. Introduction and Motivation Why on chip networks? State of the art Taxonomy Technology trends
II. Architectures for NoCs Direct vs indirect networks Topologies Standard architectures and formal properties Ad hoc networks
III. Physical network layer Wiring issues Physical routing Signalling Driver/receiver design Noise immunity Shielding
IV. Data-link layer and encoding Medium access control Data encoding Error correcting codes: theory and practice Arbitration issues
V. Switching and Routing in NoCs Packets, flits. Data forwarding schemes Routing: algorithms and routers QoS guarantees
VI. Software for NoCs Programming paradigms: shared medium vs message passing Middleware issues. layering and software encapsulation Application layer issue and network-aware compilation
VII. Tools for NoC Design Analysis and Synthesis of NoCs Present tools (Bones, Xpipes) and future outlook
VIII. On-Chip multiprocessors High-performance monolithic multiprocessors Network issues
IX. SoCs based on NoCs Examples of other design chips using NoCs
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- © Morgan Kaufmann 2006
- 20th July 2006
- Morgan Kaufmann
- eBook ISBN:
- Hardcover ISBN:
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“The design of a complex SoC requires the mastering of two major tasks: The design of the computational elements and of their interconnect. The exponentially increasing complexity and heterogeneity of future SoCs forces the designer to abandon traditional bus -based structures and to implement innovative networks-on-chip. This book, written by two leading researchers, is the first of its kind. It is a must on the bookshelf of anybody having an interest in SoC design.” — Heinrich Meyr, Professor RWTH Aachen University and Chief Scientific officer, CoWare, Inc. “This is a highly recommended, informative reference book, with high quality contents provided by the leading experts of the area.” — Professor Bashir M. Al-Hashimi, Electronic Systems Design Group, Department of Electronics and Computer Science, University of Southampton, UK “An in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions, make this book a reference for engineers involved in specification, design or evaluation of NoC architectures.” —Philippe Martin, Product Marketing Director, Arteris “Designers of Systems-on-a-Chip (SoC) are now struggling with the uncertainty of deep submicron devices and an explosion of system complexity. Networks on Chip (NoC) is a new paradigm of SoC design at the system architecture level. A protocol stack of NoC introduced in this book shows a global solution to manage the complicated design problems of SoC. This book gives a clear and systematic methodology of NoC design and will release designers from the nightmare of fights against signal integrity, reliability and variability.” — Hiroto Yasuura, Director and Professor, System LSI Research Center (SLRC), Kyushu University, Fukuoka, Japan