Networks-on-Chip
From Implementations to Programming Paradigms
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Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms. This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs.
Key Features
- Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs.
- The coherent and uniform format offers readers a clear, quick and efficient exploration of NoC design space
- Covers many novel and exciting research ideas, which encourage researchers to further delve into these topics.
- Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value.
Readership
Graduates in computer architecture, especially those whose research focuses on Networks-on-Chip, and practicing engineers in computer architecture design.
Table of Contents
- Preface
- About the Editor-in-Chief and Authors
- Editor-in-Chief
- Authors
- Part I: Prologue
- Chapter 1: Introduction
- Abstract
- 1.1 The dawn of the many-core era
- 1.2 Communication-centric cross-layer optimizations
- 1.3 A baseline design space exploration of NoCs
- 1.4 Review of NoC research
- 1.5 Trends of real processors
- 1.6 Overview of the book
- Chapter 1: Introduction
- Part II: Logic implementations
- Introduction
- Chapter 2: A single-cycle router with wing channels
- Abstract
- 2.1 Introduction
- 2.2 The router architecture
- 2.3 Microarchitecture designs
- 2.4 Experimental results
- 2.5 Chapter summary
- Chapter 3: Dynamic virtual channel routers with congestion awareness
- Abstract
- 3.1 Introduction
- 3.2 DVC with congestion awareness
- 3.3 Multiple-port shared buffer with congestion awareness
- 3.4 DVC router microarchitecture
- 3.5 HiBB router microarchitecture
- 3.6 Evaluation
- 3.7 Chapter Summary
- Chapter 4: Virtual bus structure-based network-on-chip topologies
- Abstract
- 4.1 Introduction
- 4.2 Background
- 4.3 Motivation
- 4.4 The VBON
- 4.5 Evaluation
- 4.6 Chapter summary
- Part III: Routing and flow control
- Introduction
- Chapter 5: Routing algorithms for workload consolidation
- Abstract
- 5.1 Introduction
- 5.2 Background
- 5.3 Motivation
- 5.4 Destination-based adaptive routing
- 5.5 Evaluation
- 5.6 Analysis and discussion
- 5.7 Chapter summary
- Chapter 6: Flow control for fully adaptive routing
- Abstract
- 6.1 Introduction
- 6.2 Background
- 6.3 Motivation
- 6.4 Flow control and routing designs
- 6.5 Evaluation on synthetic traffic
- 6.6 Evaluation of parsec workloads
- 6.7 Detailed analysis of flow control
- 6.8 Further discussion
- 6.9 Chapter summary
- Appendix: logical equivalence of Alg and Alg + WPF
- Chapter 7: Deadlock-free flow control for torus networks-on-chip
- Abstract
- 7.1 Introduction
- 7.2 Limitations of existing designs
- 7.3 Flit bubble flow control
- 7.4 Router microarchitecture
- 7.5 Methodology
- 7.6 Evaluation on 1D tori (rings)
- 7.7 Evaluation on 2D tori
- 7.8 Overheads: power and area
- 7.9 Discussion and related work
- 7.10 Chapter summary
- Part IV: Programming paradigms
- Introduction
- Chapter 8: Supporting cache-coherent collective communications
- Abstract
- 8.1 Introduction
- 8.2 Message combination framework
- 8.3 Bam routing
- 8.4 Router pipeline and microarchitecture
- 8.5 Evaluation
- 8.6 Power analysis
- 8.7 Related work
- 8.8 Chapter summary
- Chapter 9: Network-on-chip customizations for message passing interface primitives
- Abstract
- 9.1 Introduction
- 9.2 Background
- 9.3 Motivation
- 9.4 Communication customization architectures
- 9.5 Evaluation
- 9.6 Chapter summary
- Chapter 10: Message passing interface communication protocol optimizations
- Abstract
- 10.1 Introduction
- 10.2 Background
- 10.3 Motivation
- 10.4 Adaptive communication mechanisms
- 10.5 Evaluation
- 10.6 Chapter summary
- Part V: Epilogue
- Chapter 11: Conclusions and future work
- Abstract
- 11.1 Conclusions
- 11.2 Future work
- Chapter 11: Conclusions and future work
- Index
Product details
- No. of pages: 382
- Language: English
- Copyright: © Morgan Kaufmann 2014
- Published: November 7, 2014
- Imprint: Morgan Kaufmann
- eBook ISBN: 9780128011782
- Paperback ISBN: 9780128009796
About the Authors
Sheng Ma
Sheng Ma received the B.S. and Ph.D. degrees in computer science and technology from the National University of Defense Technology (NUDT) in 2007 and 2012, respectively. He visited the University of Toronto from Sept. 2010 to Sept. 2012. He is currently an Assistant Professor of the College of Computer, NUDT. His research interests include on-chip networks, SIMD architectures and arithmetic unit designs.
Affiliations and Expertise
Assistant Professor of the College of Computer, NUDT
Libo Huang
Libo Huang received the B.S. and Ph.D. degree in computer engineering from National University of Defense Technology, PR China, in 2005 and 2010 respectively. From 2010, he was a Lecturer with the Department of Computer Science. His research interests include computer architecture, hardware/software Codesign, VLSI design, on-chip communication. He served as the technical reviewer of several conference and journals, e.g. MEJ, IJHPSA, ICCE 2010. Since 2004, he authored more than 20 papers in internationally recognized journals and conferences
Affiliations and Expertise
Lecturer of the College of Computer, NUDT
Mingche Lai
Mingche Lai received the PhD degree in computer engineering from NUDT in 2008. Currently, he is an Associate Professor with College of Computer, NUDT, and employed to develop high-performance computer interconnection systems. Since 2008, he has also been a Faculty Member with National Key Laboratory for Parallel and Distributed Processing of China. His research interests include on-chip networks, optical communication, many-core processor architecture, hardware/software co-design. He is a member of the IEEE and ACM
Affiliations and Expertise
Assistant Professor of the College of Computer, NUDT
Wei Shi
Wei Shi received the PhD degree in computer Science from the National University of Defense Technology (NUDT) in 2010. Currently, he is an Assistant Professor of the College of Computer, NUDT, and employed to develop high-performance processors. His research interests include computer architecture, VLSI design, on-chip communication and asynchronous circuit techniques
Affiliations and Expertise
Assistant Professor of the College of Computer, NUDT
About the Editor in Chief
Zhiying Wang
Zhiying Wang received the PhD degree in electrical engineering from the National University of Defense Technology in 1988. He is currently a professor with College of Computer, NUDT. He has contributed over 10 invited chapters to book volumes, published 240 papers in archival journals and refereed conference proceedings, and delivered over 30 keynotes. His main research fields include computer architecture, computer security, VLSI design, reliable architecture, multicore memory system and asynchronous circuit. He is a member of the IEEE and ACM.
Affiliations and Expertise
Professor, Vice Dean of College of Computer, NUDT