Description

The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors. Through chapters on hardware, software, performance and modeling, Volume 3 illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors. Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.

Key Features

*Investigates current applications of network processor technology at Intel; Infineon Technologies; and NetModule. Presents current research in network processor design in three distinct areas: *Architecture at Washington University, St. Louis; Oregon Health and Science University; University of Georgia; and North Carolina State University. *Tools and Techniques at University of Texas, Austin; Academy of Sciences, China; University of Paderborn, Germany; and University of Massachusetts, Amherst. *Applications at University of California, Berkeley; Universidad Complutense de Madrid, Spain; ETH Zurich, Switzerland; Georgia Institute of Technology; Vrije Universiteit, the Netherlands; and Universiteit Leiden, the Netherlands.

Readership

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Table of Contents

1. Network Processors: New Horizons Patrick Crowley, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk 2. Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches Patrick Crowley 3. Efficient Packet Classification with Digest Caches Francis Chang, Wu-chang Feng, Wu-chi Feng, Kang Li 4 Towards a Flexible Network Processor Interface for RapidIO, Hypertransport, and PCI-Express Christian Sauer, Matthias Gries, Kurt Keutzer, Jose Ignacio Gomez 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla, Nitin Borkar 6. A Hardware Platform for Network Intrusion Detection and Prevention Chris Clark,Wenke Lee, David Schimmel, Didier Contis, Mohamed Koné, Ashley Thomas 7. Packet Processing on a SIMD Stream Processor Jathin S. Rai, Yu-Kuen Lai, Gregory T. Byrd 8. A Programming Environment for Packet-Processing Systems: Design Considerations Harrick Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson,Roy Ju, Aaron Kunze, Ruiqi Lian 9. RNOS—A Middleware Platform for Low-Cost Packet-Processing Devices Jonas Greutert, Lothar Thiele 10. On the Feasibility of Using Network Processors for DNA Queries Herbert Bos, Kaiming Huang 11. Pipeline Task Scheduling on Network Processors Mark A. Franklin, Seema Datar 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs Matthias Grünewald, Jörg-Christian

Details

No. of pages:
336
Language:
English
Copyright:
© 2005
Published:
Imprint:
Morgan Kaufmann
Print ISBN:
9780120884766
Electronic ISBN:
9780080512501

About the editors

Patrick Crowley

Patrick Crowley is an associate Professor in the Department of Computer Science & Engineering at Washington University in St. Louis, Missouri. His research interests are in computer and network systems architecture, with a current focus on the design of programmable embedded network systems and the invention of superior network monitoring and security techniques. He co-founded the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, and co-edited the three-book series, Network Processor Design. He serves as Associate Editor of the IEEE/ACM Transactions on Networking. In 2007, Crowley was chosen to join the DARPA Computer Science Study Group.

Peter Onufryk

Peter Z. Onufryk received his B.S.E.E. from Rutgers University, M.S.E.E. from Purdue University, and Ph.D. in Electrical and Computer Engineering from Rutgers University. He is currently a director in the Internetworking Products Division at Integrated Device Technology, Inc. where he is responsible for architecture definition and validation of communications products. Before joining IDT, Peter was a researcher for thirteen years at AT&T Labs - Research (formally AT&T Bell Labs) where he worked on communications systems and parallel computer architectures. These included a number of parallel, cache-coherent multiprocessor and dataflow based machines that were targeted towards high performance military systems. Other work there focused on packet telephony and early network processors. Onufryk is a member of the IEEE. He was an organizer and program committee member of the HPCA8 Workshop on Network Processors 2002. Peter was the architect of four communications processors as well as numerous ASICs, boards, and systems.