Multicore Software Development Techniques - 1st Edition - ISBN: 9780128009581, 9780128010372

Multicore Software Development Techniques

1st Edition

Applications, Tips, and Tricks

Authors: Robert Oshana
eBook ISBN: 9780128010372
Paperback ISBN: 9780128009581
Imprint: Newnes
Published Date: 25th November 2015
Page Count: 236
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Description

This book provides a set of practical processes and techniques used for multicore software development.  It is written with a focus on solving day to day problems using practical tips and tricks and industry case studies to reinforce the key concepts in multicore software development.

Coverage includes:

  • The multicore landscape
  • Principles of parallel computing
  • Multicore SoC architectures
  • Multicore programming models
  • The Multicore development process
  • Multicore programming with threads
  • Concurrency abstraction layers
  • Debugging Multicore Systems
  • Practical techniques for getting started in multicore development
  • Case Studies in Multicore Systems Development
  • Sample code to reinforce many of the concepts discussed

Key Features

  • Presents the ‘nuts and bolts’ of programming a multicore system
  • Provides a short-format book on the practical processes and techniques used in multicore software development
  • Covers practical tips, tricks and industry case studies to enhance the learning process

Readership

Software architects and programmers, embedded system architects, hardware designers and engineers

Table of Contents

  • Chapter 1. Principles of Parallel Computing
    • Abstract
    • 1.1 Concurrency versus Parallelism
    • 1.2 Symmetric and Asymmetric Multiprocessing
    • 1.3 Parallelism Saves Power
    • 1.4 Key Challenges of Parallel Computing
  • Chapter 2. Parallelism in All of Its Forms
    • Abstract
    • 2.1 Bit-Level Parallelism
    • 2.2 Instruction-Level Parallelism (ILP)
    • 2.3 Simultaneous Multithreading
    • 2.4 Single Instruction, Multiple Data (SIMD)
    • 2.5 Data Parallelism
    • 2.6 Task Parallelism
    • 2.7 Acceleration and Offload Engines
  • Chapter 3. Multicore System Architectures
    • Abstract
    • 3.1 Shared Memory Multicore Systems
    • 3.2 Cache Coherency
    • 3.3 Shared Data Synchronization
    • 3.4 Distributed Memory
    • 3.5 Symmetric Multiprocessing
    • 3.6 Asymmetric Multiprocessing
    • 3.7 Hybrid Approaches
    • 3.8 Speaking of Cores
    • 3.9 Graphical Processing Units (GPU)
    • 3.10 Putting It All Together
  • Chapter 4. Multicore Software Architectures
    • Abstract
    • 4.1 Multicore Software Architectures
    • 4.2 A Decision Tree Approach to Selecting a Multicore Architecture
  • Chapter 5. Multicore Software Development Process
    • Abstract
    • 5.1 Multicore Programming Models
  • Chapter 6. Putting it All Together, A Case Study of Multicore Development
    • Abstract
    • 6.1 Multiple-Single-Cores
    • 6.2 Cooperating-Multiple-Cores
    • 6.3 Getting Started
    • 6.4 System Requirements
  • Chapter 7. Multicore Virtualization
    • Abstract
    • 7.1 Hypervisor Classifications
    • 7.2 Virtualization Use Cases for Multicore
    • 7.3 Linux Hypervisors
    • 7.4 Virtual Networking in Multicore
    • 7.5 I/O Activity in a Virtualized Environment
    • 7.6 Direct Device Assignment
  • Chapter 8. Performance and Optimization of Multicore Systems
    • Abstract
    • 8.1 Select the Right “Core” for Your Multicore
    • 8.2 Improve Serial Performance before Migrating to Multicore (Especially ILP)
    • 8.3 Achieve Proper Load Balancing (SMP Linux) and Scheduling
    • 8.4 Improve Data Locality
    • 8.5 Reduce or Eliminate False Sharing
    • 8.6 Use Affinity Scheduling When Necessary
    • 8.7 Apply the Proper Lock Granularity and Frequency
    • 8.8 Remove Sync Barriers Where Possible
    • 8.9 Minimize Communication Latencies
    • 8.10 Use Thread Pools
    • 8.11 Manage Thread Count
    • 8.12 Stay Out of the Kernel If at all Possible
    • 8.13 Use Parallel Libraries (pthreads, OpenMP, etc.)
  • Chapter 9. Sequential to Parallel Migration of Software Applications
    • Abstract
    • 9.1 Step 1: Understand Requirements
    • 9.2 Step 2: Sequential Analysis
    • 9.3 Step 3: Exploration
    • 9.4 Step 4: Code Optimization and Tuning
    • 9.5 Image Processing Example
    • 9.6 Step 2: Sequential Analysis
    • 9.7 Step 3: Exploration
    • 9.8 Step 4: Optimization and Tuning
    • 9.9 Data Parallel; First Attempt
    • 9.10 Data Parallel—Second Try
    • 9.11 Task Parallel—Third Try
    • 9.12 Exploration Results
    • 9.13 Tuning
    • 9.14 Data Parallel—Third Try
    • 9.15 Data Parallel—Third Results
    • 9.16 Data Parallel—Fourth Try
    • 9.17 Data Parallel—Work Queues
    • 9.18 Going Too Far?
  • Chapter 10. Concurrency Abstractions
    • Abstract
    • 10.1 Language Extensions Example—OpenMP
    • 10.2 Framework Example—OpenCL
    • 10.3 Libraries Example—Thread Building Libraries
    • 10.4 Thread Safety
    • 10.5 Message Passing Multicore Models—MPI and MCAPI
    • 10.6 Language Support
    • Additional Reading
  • Appendix A. Source Code Examples
    • Matrix Multiply – Naïve Version (Not Cache Friendly)
    • Matrix Multiply—Cache Friendly Version
    • Primes Code with Race Conditions
    • Primes Code with Race Conditions FIXED
    • Conway’s Game of Life Unoptimized
    • Conway’s Game of Life Optimized

Details

No. of pages:
236
Language:
English
Copyright:
© Newnes 2016
Published:
Imprint:
Newnes
eBook ISBN:
9780128010372
Paperback ISBN:
9780128009581

About the Author

Robert Oshana

Robert Oshana has over 30 years of experience in the embedded software industry, primarily focused on embedded and real-time systems for the defence industry and semiconductor industries. He has BSEE, MSEE, MSCS, and MBA degrees and is a Senior Member of IEEE. Rob is an international speaker and has over 100 presentations and publications in various technology fields and has written several books on embedded software technology. Rob is an adjunct professor at Southern Methodist University and University of Texas and is a Distinguished Member of Technical Staff and Director of Software Enablement for Digital Networking at Freescale Semiconductor.

Affiliations and Expertise

Freescale, Austin, TX, USA