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2. Behavior and Concurrency
3. The Untimed Model of Computation
4. The Synchronous Model of Computation
5. The Timed Model of Computation
6. MoC Interfaces
7. Tightly Coupled Process Networks
8. Nondeterminism and Probability
10. Concluding Remarks
Over the last decade, advances in the semiconductor fabrication process have led to the realization of true system-on-a-chip devices. But the theories, methods and tools for designing, integrating and verifying these complex systems have not kept pace with our ability to build them. System level design is a critical component in the search for methods to develop designs more productively. However, there are a number of challenges that must be overcome in order to implement system level modeling.
This book directly addresses that need by developing organizing principles for understanding, assessing, and comparing the different models of computation necessary for system level modeling. Dr. Axel Jantsch identifies the representation of time as the essential feature for distinguishing these models. After developing this conceptual framework, he presents a single formalism for representing very different models, allowing them to be easily compared. As a result, designers, students, and researchers are able to identify the role and the features of the "right" model of computation for the task at hand.
Offers a unique and significant contribution to the emerging field of models of computation
Presents a systematic way of understanding and applying different Models of Computation to embedded systems and SoC design
*Offers insights and illustrative examples for practioners, researchers and students of complex electronic systems design.
Digital Systems Designers; Embedded Systems Designers, System-on-a-chip designers, graduate students, researchers
- No. of pages:
- © Morgan Kaufmann 2003
- 2nd June 2003
- Morgan Kaufmann
- Hardcover ISBN:
- Paperback ISBN:
- eBook ISBN:
"I recommend this book highly to those who are new to this subject or who need to better understand its formal underpinnings. System level tool developers will find these concepts an excellent basis for determining which modeling approaches will be supported and why. Jantsch's book is a major advance in the material available to students, researchers and practitioners alike in this important and vital area."
-From the foreword by Grant Martin, Fellow, Cadence Laboratories
"This book is a groundbreaking first, offering a comparative analysis of families of methods. It will be extremely valuable to anyone who thinks about modeling and worries about how to select from competing approaches."
-Edward A. Lee, University of California, Berkeley
"Anyone interested in computational models for the design of embedded systems will find this outstanding book most helpful. It provides a close look at architectural issues that are fundamental for designing SoCs now and in the near future."
-John Vacca, former computer security official (CSO) for NASA's space station program
Axel Jantsch received a Dipl.Ing. in 1988 and a Dr. Tech. degree in 1992 from the Technical University of Vienna. Between 1993 and 1995 he received the Alfred Schrödinger scholarship from the Austrian Science Foundation as a guest researcher at the Royal Institute of Technology (KTH) in Stockholm. From 1995 through 1997 he was with Siemens Austria in Vienna as a system validation engineer. From 1997 to 2002 he was as Associate Professor at KTH, and since December 2002 he has served as Professor in Electronic System Design. Jantsch has published in the areas of VLSI design and synthesis, system level specification, modeling and validation, HW/SW codesign and cosynthesis, reconfigurable computing, processor design and networks-on-chip. For several years he has been a program committee member of FDL and DATE conferences. He has served as TPC chair of SSDL/FDL 2000 and is Subject Area Editor for the Journal of Systems Architecture. At KTH, Jantsch is heading a number of research projects in the areas of system level specification, design, synthesis, validation and network-on-chip architecture. From 1999 to 2002, he served as program manager of the Swedish research program Integrated Electronic Systems with a 4-year budget of 12 million Euro.
Royal Institute of Technology, Stockholm, Sweden
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