Millimeter-Wave Digitally Intensive Frequency Generation in CMOS

This book describes the digitally intensive time-domain architectures and techniques applied to millimeter-wave frequency synthesis, with the objective of improving performance and reducing the cost of implementation. Coverage includes system architecture, system level modeling, critical building block design, and digital calibration techniques, making it highly suitable for those who want to learn about mm-wave frequency generation for communication and radar applications, integrated circuit implementation, and time-domain circuit and system techniques.

• Highlights the challenges of frequency synthesis at mm-wave band using CMOS technology
• Compares the various approaches for mm-wave frequency generation (pros and cons)
• Introduces the digitally intensive synthesizer approach and its advantages
• Discusses the proper partitioning of the digitally intensive mm-wave frequency synthesizer into mm-wave, RF, analog, digital and software components
• Provides detailed design techniques from system level to circuit level
• Addresses system modeling, simulation techniques, design-for-test, and layout issues
• Demonstrates the use of time-domain techniques for high-performance mm-wave frequency synthesis

University researchers, R&D engineers in industry, RFIC design engineers, and graduate students who want to learn about mm-wave frequency generation for communication and radar applications, integrated circuit implementation, and time-domain circuit and system techniques.

• Preface
• List of Abbreviations
• Chapter 1. Introduction
  • 1.1 Motivation
  • 1.2 Design Challenges
  • References
• Chapter 2. Millimeter-Wave Frequency Synthesizers
  • 2.1 Frequency Synthesizer Fundamentals
  • 2.2 Phase-Locked Loop
  • 2.3 Millimeter-Wave PLL Architectures
  • 2.4 Summary
  • References
• Chapter 3. Circuit Design Techniques for mm-Wave Frequency Synthesizer
  • 3.1 Wideband Oscillator
  • 3.2 High-Frequency Divider
  • 3.3 Frequency Multiplier
  • 3.4 Summary
  • References
• Chapter 4. All-Digital Phase-Locked Loop
  • 4.1 Phase-Domain Operation
  • 4.2 Reference Clock Retiming
  • 4.3 DCO Gain Normalization and Estimation
  • 4.4 Loop Gain Factor and Gear Shifting of the PLL Gain
  • 4.5 PLL Frequency Response
  • 4.6 Noise and Error Sources
  • 4.7 Behavioral Modeling and Simulation Approach
  • 4.8 Summary
  • References
• Chapter 5. Millimeter-Wave Digitally Controlled Oscillator
  • 5.1 From Low-Gigahertz DCOs to mm-Wave DCOs
  • 5.2 Reconfigurable Resonator with Distributed Metal Capacitors
  • 5.3 Fine-Tuning Techniques to Achieve High-Frequency Resolution
  • 5.4 Example Implementation of 60-GHz DCOs
  • 5.5 Summary
  • References
• Chapter 6. Application: A 60-GHz All-Digital PLL for FMCW Transmitter Applications
  • 6.1 Design Specification
  • 6.2 Multi-Rate ADPLL-Based Frequency Modulator
  • 6.3 DCO Interfacing
  • 6.4 Divider Chain Design
  • 6.5 TDC Design and Calibration
  • 6.6 Reference Slicer Design
  • 6.7 Phase Error Generation and Glitch Removal
  • 6.8 Top-Level Floor Plan Considerations for mm-Wave ADPLL
  • 6.9 Experiment Results for 60-GHz ADPLL
  • 6.10 Summary
  • References
• Chapter 7. Digital Techniques for Higher RF Performance
  • 7.1 Frequency Tuning Nonlinearity in a Multibank DCO
  • 7.2 Multibank DCO Gain Calibration and Linearization
  • 7.3 Mismatch Calibration of the Fine-Tuning Bank
  • 7.4 Synchronization in a Multirate System
  • 7.5 Experimental Results of FMCW Transmitter
  • 7.6 Summary
  • References
• Chapter 8. Design for Test of the mm-Wave ADPLL
  • 8.1 Testing Challenges for the RF Synthesizer
  • 8.2 Critical Signals in ADPLL for DFT and DFC
  • 8.3 DFT Techniques for ADPLL
  • 8.4 Measurement Setup and Procedures
  • 8.5 Summary
  • References
• Index