Interconnection Networks
Description
Key Features
* Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs
* Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks
* Focuses on issues critical to designers
Readership
Table of Contents
- Foreword
Foreword to the First Printing
Preface
Chapter 1 - Introduction
Chapter 2 - Message Switching Layer
Chapter 3 - Deadlock, Livelock, and Starvation
Chapter 4 - Routing Algorithms
Chapter 5 - CollectiveCommunicationSupport
Chapter 6 - Fault-Tolerant Routing
Chapter 7 - Network Architectures
Chapter 8 - Messaging Layer Software
Chapter 9 - Performance Evaluation
Appendix A - Formal Definitions for Deadlock Avoidance
Appendix B - Acronyms
References
Index
Product details
- No. of pages: 624
- Language: English
- Copyright: © Morgan Kaufmann 2002
- Published: July 29, 2002
- Imprint: Morgan Kaufmann
- eBook ISBN: 9780080508993
- Hardcover ISBN: 9781558608528
About the Authors
Jose Duato
His current research interests include high-speed interconnects, multiprocessor architectures, cluster architectures, and IP routers. Dr. Duato proposed the first theory of deadlock-free adaptive routing for wormhole networks. This theory has been used in the design of the routing algorithms for the MIT Reliable Router, the Cray T3E router, and the on-chip router of the Alpha 21364 microprocessor. Dr. Duato is currently collaborating with IBM on the design of the interconnection network for the IBM BlueGene/L supercomputer, and on the next generation of the IBM PRIZMA switch for IP routers.
Dr. Duato served as a member of the editorial board of IEEE Transactions on Parallel and Distributed Systems and he is currently serving as associate editor of IEEE Transactions on Computers. He has been the General Co-Chair for the 2001 International Conference on Parallel Processing. Also, he served as Co-Chair, member of the Steering Committee, Vice-Chair, or member of the Program Committee in more than 30 conferences, including the most prestigious conferences in his field (HPCA, ISCA, IPPS/SPDP, ICPP, ICDCS, Europar, HiPC).
Affiliations and Expertise
Sudhakar Yalamanchili
University of Texas at Austin in 1980 and 1984, respectively.
He was a Senior and then Principal Research Scientist at the Honeywell Systems and Research Center in Minneapolis from 1984 to 1989 where he was the Principal Investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. Since 1989 he has been on the faculty at the Georgia Institute of Technology where he is currently Professor of Electrical and Computer Engineering. He is the author of the texts VHDL Starter's Guide and Introductory VHDL: From Simulation to Synthesis from Prentice Hall (2000). His current research interests are lay in the intersection of system area networks, configurable computing technologies, and high speed switching and routing. His current projects focus on the development of high-speed switching substrates for supporting data intensive communication.
Dr. Yalamanchili is a member of the ACM and Senior Member of the IEEE. He has served as an associate editor for the IEEE Transactions on Parallel and Distributed Systems and IEEE
Transactions on Computers and serves in program committees for international conferences in the area of high performance computing systems.
Affiliations and Expertise
Lionel Ni
for authoring outstanding papers. His paper (with Chris Glass) ``The Turn Model for Adaptive Routing'' was selected as one of the 41 most significant impact papers in the last 25 years in computer architecture in 1998. He also won the Michigan State University Distinguished Faculty Award in 1994.
Dr. Ni has served as an associate editor for the IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers.