Interconnection Networks
1st Edition
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Table of Contents
Foreword
Foreword to the First Printing
Preface
Chapter 1 - Introduction
Chapter 2 - Message Switching Layer
Chapter 3 - Deadlock, Livelock, and Starvation
Chapter 4 - Routing Algorithms
Chapter 5 - CollectiveCommunicationSupport
Chapter 6 - Fault-Tolerant Routing
Chapter 7 - Network Architectures
Chapter 8 - Messaging Layer Software
Chapter 9 - Performance Evaluation
Appendix A - Formal Definitions for Deadlock Avoidance
Appendix B - Acronyms
References
Index
Description
The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems.
Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems.
In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature.
Key Features
- Gives a coherent, comprehensive treatment of the entire field
* Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs
* Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks
* Focuses on issues critical to designers
Readership
Practitioners, researchers and students in Computer Architecture and Digital System Design.
Details
- No. of pages:
- 624
- Language:
- English
- Copyright:
- © Morgan Kaufmann 2002
- Published:
- 29th July 2002
- Imprint:
- Morgan Kaufmann
- eBook ISBN:
- 9780080508993
- Hardcover ISBN:
- 9781558608528
Reviews
@qu:"This book, for the first time, makes the technology of interconnection networks accessible to the engineering student and the practicing engineer. The authors are three key members of the research community and are responsible for developing much of the technology described. Their unique knowledge and rare insight into the material make for a technically rich treatment that brings together the best of many research papers and fills in the gaps by putting the work into context. In an era when digital systems design is dominated by interconnect, every digital designer needs to understand the concepts of topology, routing, and flow control on which interconnection networks are based. There is no better way for an engineer to come up to speed on interconnection networks than by reading this book."
@source:—From the foreword by Bill Dally, Professor, Stanford University
Ratings and Reviews
About the Authors
Jose Duato
José Duato received MS and PhD degrees in electrical engineering from the Universidad Politecnica de Valencia, Spain, in 1981 and 1985. Currently, Dr. Duato is Professor in the Department of Computer Engineering (DISCA), and adjunct professor in the Department of Computer and Information Science, The Ohio State University.
His current research interests include high-speed interconnects, multiprocessor architectures, cluster architectures, and IP routers. Dr. Duato proposed the first theory of deadlock-free adaptive routing for wormhole networks. This theory has been used in the design of the routing algorithms for the MIT Reliable Router, the Cray T3E router, and the on-chip router of the Alpha 21364 microprocessor. Dr. Duato is currently collaborating with IBM on the design of the interconnection network for the IBM BlueGene/L supercomputer, and on the next generation of the IBM PRIZMA switch for IP routers.
Dr. Duato served as a member of the editorial board of IEEE Transactions on Parallel and Distributed Systems and he is currently serving as associate editor of IEEE Transactions on Computers. He has been the General Co-Chair for the 2001 International Conference on Parallel Processing. Also, he served as Co-Chair, member of the Steering Committee, Vice-Chair, or member of the Program Committee in more than 30 conferences, including the most prestigious conferences in his field (HPCA, ISCA, IPPS/SPDP, ICPP, ICDCS, Europar, HiPC).
Affiliations and Expertise
Ohio State University
Sudhakar Yalamanchili
Sudhakar Yalamanchili received the BE degree in Electronics from Bangalore University, India in 1978, and the MS and PhD degrees in Electrical and Computer Engineering from the
University of Texas at Austin in 1980 and 1984, respectively.
He was a Senior and then Principal Research Scientist at the Honeywell Systems and Research Center in Minneapolis from 1984 to 1989 where he was the Principal Investigator for projects in the design and analysis of multiprocessor architectures for embedded applications. Since 1989 he has been on the faculty at the Georgia Institute of Technology where he is currently Professor of Electrical and Computer Engineering. He is the author of the texts VHDL Starter's Guide and Introductory VHDL: From Simulation to Synthesis from Prentice Hall (2000). His current research interests are lay in the intersection of system area networks, configurable computing technologies, and high speed switching and routing. His current projects focus on the development of high-speed switching substrates for supporting data intensive communication.
Dr. Yalamanchili is a member of the ACM and Senior Member of the IEEE. He has served as an associate editor for the IEEE Transactions on Parallel and Distributed Systems and IEEE
Transactions on Computers and serves in program committees for international conferences in the area of high performance computing systems.
Affiliations and Expertise
Georgia Institute of Technology
Lionel Ni
Lionel M. Ni earned his PhD degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 1980. He is Professor in the Computer Science and Engineering Department at Michigan State University. His research interests include parallel architectures, distributed systems, high-speed networks, and pervasive computing. A fellow of IEEE, Dr. Ni has chaired many professional conferences and received a number of awards
for authoring outstanding papers. His paper (with Chris Glass) ``The Turn Model for Adaptive Routing'' was selected as one of the 41 most significant impact papers in the last 25 years in computer architecture in 1998. He also won the Michigan State University Distinguished Faculty Award in 1994.
Dr. Ni has served as an associate editor for the IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers.
Affiliations and Expertise
Professor and Head of Computer Science Department at Hong Kong University of Science and Technology
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