High Performance Parallelism Pearls Volume One

1st Edition

Multicore and Many-core Programming Approaches

Authors: James Reinders James Jeffers
Paperback ISBN: 9780128021187
eBook ISBN: 9780128021996
Imprint: Morgan Kaufmann
Published Date: 3rd November 2014
Page Count: 600
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High Performance Parallelism Pearls shows how to leverage parallelism on processors and coprocessors with the same programming – illustrating the most effective ways to better tap the computational potential of systems with Intel Xeon Phi coprocessors and Intel Xeon processors or other multicore processors. The book includes examples of successful programming efforts, drawn from across industries and domains such as chemistry, engineering, and environmental science. Each chapter in this edited work includes detailed explanations of the programming techniques used, while showing high performance results on both Intel Xeon Phi coprocessors and multicore processors. Learn from dozens of new examples and case studies illustrating "success stories" demonstrating not just the features of these powerful systems, but also how to leverage parallelism across these heterogeneous systems.

Key Features

  • Promotes consistent standards-based programming, showing in detail how to code for high performance on multicore processors and Intel® Xeon Phi™
  • Examples from multiple vertical domains illustrating parallel optimizations to modernize real-world codes
  • Source code available for download to facilitate further exploration



software engineers in high-performance computing and system developers in vertical domains hoping to leverage HPC

Table of Contents

  • Acknowledgments
  • Foreword

    • Humongous computing needs: Science years in the making
    • Open standards
    • Keen on many-core architecture
    • Xeon Phi is born: Many cores, excellent vector ISA
    • Learn highly scalable parallel programming
    • Future demands grow: Programming models matter
  • Preface

    • Inspired by 61 cores: A new era in programming
  • Chapter 1: Introduction

    • Abstract
    • Learning from successful experiences
    • Code modernization
    • Modernize with concurrent algorithms
    • Modernize with vectorization and data locality
    • Understanding power usage
    • ISPC and OpenCL anyone?
    • Intel Xeon Phi coprocessor specific
    • Many-core, neo-heterogeneous
    • No “Xeon Phi” in the title, neo-heterogeneous programming
    • The future of many-core
    • Downloads
  • Chapter 2: From “Correct” to “Correct & Efficient”: A Hydro2D Case Study with Godunov’s Scheme

    • Abstract
    • Scientific computing on contemporary computers
    • A numerical method for shock hydrodynamics
    • Features of modern architectures
    • Paths to performance
    • Summary
  • Chapter 3: Better Concurrency and SIMD on HBM

    • Abstract
    • The application: HIROMB-BOOS-Model
    • Key usage: DMI
    • HBM execution profile
    • Overview for the optimization of HBM
    • Data structures: Locality done right
    • Thread parallelism in HBM
    • Data parallelism: SIMD vectorization
    • Results
    • Profiling details
    • Scaling on processor vs. coprocessor
    • Contiguous attribute
    • Summary
  • Chapter 4: Optimizing for Reacting Navier-Stokes Equations

    • Abstract
    • Getting started
    • Version 1.0: Baseline
    • Version 2.0: ThreadBox
    • Versi


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© Morgan Kaufmann 2015
Morgan Kaufmann
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About the Author

James Reinders

James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world’s first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012.

Affiliations and Expertise

Director and Programming Model Architect, Intel Corporation

James Jeffers

Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel ® MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years.

Affiliations and Expertise

Principal Engineer and Visualization Lead, Intel Corporation


"This book will make it much easier in general to exploit high levels of parallelism including programming optimally for the Intel Xeon Phi products. The common programming methodology between the Xeon and Xeon Phi families is good news for the entire scientific and engineering community; the same programming can realize parallel scaling and vectorization for both multicore and many-core." –-from the Foreword by Sverre Jarp, CERN Openlab CTO