Heterogeneous System Architecture

Heterogeneous System Architecture

A New Compute Platform Infrastructure

1st Edition - November 20, 2015

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  • Author: Wen-mei Hwu
  • eBook ISBN: 9780128008010
  • Paperback ISBN: 9780128003862

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Heterogeneous Systems Architecture - a new compute platform infrastructure presents a next-generation hardware platform, and associated software, that allows processors of different types to work efficiently and cooperatively in shared memory from a single source program. HSA also defines a virtual ISA for parallel routines or kernels, which is vendor and ISA independent thus enabling single source programs to execute across any HSA compliant heterogeneous processer from those used in smartphones to supercomputers. The book begins with an overview of the evolution of heterogeneous parallel processing, associated problems, and how they are overcome with HSA. Later chapters provide a deeper perspective on topics such as the runtime, memory model, queuing, context switching, the architected queuing language, simulators, and tool chains. Finally, three real world examples are presented, which provide an early demonstration of how HSA can deliver significantly higher performance thru C++ based applications. Contributing authors are HSA Foundation members who are experts from both academia and industry. Some of these distinguished authors are listed here in alphabetical order: Yeh-Ching Chung, Benedict R. Gaster, Juan Gómez-Luna, Derek Hower, Lee Howes, Shih-Hao HungThomas B. Jablin, David Kaeli,Phil Rogers, Ben Sander, I-Jui (Ray) Sung.

Key Features

  • Provides clear and concise explanations of key HSA concepts and fundamentals by expert HSA Specification contributors
  • Explains how performance-bound programming algorithms and application types can be significantly optimized by utilizing HSA hardware and software features
  • Presents HSA simply, clearly, and concisely without reading the detailed HSA Specification documents
  • Demonstrates ideal mapping of processing resources from CPUs to many other heterogeneous processors that comply with HSA Specifications


Corporate software application developers; computer science researchers at universities; students in computer architecture, distributed computing, or software engineering courses.

Table of Contents

    • Foreword
    • Preface
    • About the Contributing Authors
    • Chapter 1: Introduction
      • Abstract
    • Chapter 2: HSA Overview
      • Abstract
      • 2.1 A Short History of GPU Computing: The Problems That Are Solved by HSA
      • 2.2 The Pillars of HSA
      • 2.3 The HSA Specifications
      • 2.4 HSA Software
      • 2.5 The HSA Foundation
      • 2.6 Summary
    • Chapter 3: HSAIL - Virtual Parallel ISA
      • Abstract
      • 3.1 Introduction
      • 3.2 Sample Compilation Flow
      • 3.3 HSAIL Execution Model
      • 3.4 A Tour of the HSAIL Instruction Set
      • 3.5 HSAIL Machine Models and Profiles
      • 3.6 HSAIL Compilation Flow
      • 3.7 HSAIL Compilation Tools
      • 3.8 Conclusion
    • Chapter 4: HSA Runtime
      • Abstract
      • 4.1 Introduction
      • 4.2 The HSA Core Runtime API
      • 4.3 HSA Runtime Extensions
      • 4.4 Conclusion
    • Chapter 5: HSA Memory Model
      • Abstract
      • 5.1 Introduction
      • 5.2 HSA Memory Structure
      • 5.3 HSA Memory Consistency Basics
      • 5.4 Advanced Consistency in the HSA Memory Model
      • 5.5 Conclusions
    • Chapter 6: HSA Queuing Model
      • Abstract
      • 6.1 Introduction
      • 6.2 User Mode Queues
      • 6.3 Architected Queuing Language
      • 6.4 Packet Submission and Scheduling
      • 6.5 Conclusions
    • Chapter 7: Compiler Technology
      • Abstract
      • 7.1 Introduction
      • 7.2 A Brief Introduction to C++ AMP
      • 7.3 HSA as a Compiler Target
      • 7.4 Mapping Key C++ AMP Constructs to HSA
      • 7.5 C++ AMP Compilation Flow
      • 7.6 Compiled C++ AMP Code
      • 7.7 Compiler Support for Tiling in C++AMP
      • 7.8 Memory Segment Annotation
      • 7.9 Towards Generic C++ for HSA
      • 7.10 Compiler Support for Platform Atomics
      • 7.11 Compiler Support for New/Delete Operators
      • 7.12 Conclusion
    • Chapter 8: Application Use Cases: Platform Atomics
      • Abstract
      • Acknowledgment
      • 8.1 Introduction
      • 8.2 Atomics in HSA
      • 8.3 Task Queue System
      • 8.4 Breadth-First Search
      • 8.5 Data Layout Conversion
      • 8.6 Conclusions
    • Chapter 9: HSA Simulators
      • Abstract
      • 9.1 Simulating HSA in Multi2Sim
      • 9.2 Emulating HSA with HSAemu
      • 9.3 SoftHSA Simulator
    • Index

Product details

  • No. of pages: 206
  • Language: English
  • Copyright: © Morgan Kaufmann 2015
  • Published: November 20, 2015
  • Imprint: Morgan Kaufmann
  • eBook ISBN: 9780128008010
  • Paperback ISBN: 9780128003862

About the Author

Wen-mei Hwu

Wen-mei Hwu
Wen-mei W. Hwu is a Professor and holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. His research interests are in the area of architecture, implementation, compilation, and algorithms for parallel computing. He is the chief scientist of Parallel Computing Institute and director of the IMPACT research group (www.impact.crhc.illinois.edu). He is a co-founder and CTO of MulticoreWare. For his contributions in research and teaching, he received the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, the ISCA Influential Paper Award, the IEEE Computer Society B. R. Rau Award and the Distinguished Alumni Award in Computer Science of the University of California, Berkeley. He is a fellow of IEEE and ACM. He directs the UIUC CUDA Center of Excellence and serves as one of the principal investigators of the NSF Blue Waters Petascale computer project. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.

Affiliations and Expertise

CTO, MulticoreWare and professor specializing in compiler design, computer architecture, microarchitecture, and parallel processing, University of Illinois at Urbana-Champaign, USA

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