Formal Verification

Formal Verification

An Essential Toolkit for Modern VLSI Design

1st Edition - July 24, 2015
This is the Latest Edition
  • Authors: Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar
  • eBook ISBN: 9780128008157
  • Paperback ISBN: 9780128007273

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Description

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.

Key Features

  • Learn formal verification algorithms to gain full coverage without exhaustive simulation
  • Understand formal verification tools and how they differ from simulation tools
  • Create instant test benches to gain insight into how models work and find initial bugs
  • Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems

Readership

Professional engineers involved in chip design or verification

Table of Contents

    • Foreword for “Formal Verification: An Essential Toolkit for Modern VLSI Design”
    • Acknowledgments
    • Chapter 1. Formal verification: From dreams to reality
      • What is FV?
      • Why This Book?
      • A Motivating Anecdote
      • FV: The Next Level of Depth
      • The Emergence of Practical FV
      • Challenges in Implementing FV
      • Amplifying the Power of Formal
      • Getting the Most Out of This Book
      • Practical Tips from This Chapter
      • Further Reading
    • Chapter 2. Basic formal verification algorithms
      • Formal Verification (FV) in the Validation Process
      • Comparing Specifications
      • Formalizing Operation Definitions
      • Boolean Algebra Notation
      • BDDs
      • Boolean Satisfiability
      • Chapter Summary
      • Further Reading
    • Chapter 3. Introduction to systemverilog assertions
      • Basic Assertion Concepts
      • Immediate Assertions
      • Sequences, Properties, and Concurrent Assertions
      • Summary
      • Further Reading
    • Chapter 4. Formal property verification
      • What is FPV?
      • Example for this Chapter: Combination Lock
      • Bringing Up a Basic FPV Environment
      • How is FPV Different from Simulation?
      • Summary
      • Further Reading
    • Chapter 5. Effective FPV for design exercise
      • Example for This Chapter: Traffic Light Controller
      • Creating a Design Exercise Plan
      • Setting Up the Design Exercise FPV Environment
      • Wiggling the Design
      • Exploring More Interesting Behaviors
      • Removing Simplifications and Exploring More Behaviors
      • Summary
      • Further Reading
    • Chapter 6. Effective FPV for verification
      • Deciding on Your FPV Goals
      • Staging Your FPV Efforts
      • Example for this Chapter: Simple ALU
      • Understanding the Design
      • Creating the FPV Verification Plan
      • Removing Simplifications and Exploring More Behaviors
      • Summary
      • Further Reading
    • Chapter 7. FPV “Apps” for specific SOC problems
      • Reusable Protocol Verification
      • Unreachable Coverage Elimination
      • Connectivity Verification
      • Control Register Verification
      • Post-Silicon Debug
      • Summary
      • Further Reading
    • Chapter 8. Formal equivalence verification
      • Types of Equivalence to Check
      • FEV Use Cases
      • Running FEV
      • Additional FEV Challenges
      • Summary
      • Further Reading
    • Chapter 9. Formal verification’s greatest bloopers: The danger of false positives
      • Misuse of the SVA Language
      • Vacuity Issues
      • Implicit or Unstated Assumptions
      • Division of Labor
      • Summary
      • Further Reading
    • Chapter 10. Dealing with complexity
      • Design State and Associated Complexity
      • Example for this Chapter: Memory Controller
      • Observing Complexity Issues
      • Simple Techniques for Convergence
      • Helper Assumptions … and Not-So-Helpful Assumptions
      • Generalizing Analysis Using Free Variables
      • Abstraction Models for Complexity Reduction
      • Summary
      • Further Reading
    • Chapter 11. Your new FV-aware lifestyle
      • Uses of FV
      • Getting Started
      • Making Your Manager Happy
      • What Do FVers Really Do?
      • Summary
      • Further Reading
    • Index

Product details

  • No. of pages: 408
  • Language: English
  • Copyright: © Morgan Kaufmann 2015
  • Published: July 24, 2015
  • Imprint: Morgan Kaufmann
  • eBook ISBN: 9780128008157
  • Paperback ISBN: 9780128007273
  • About the Authors

    Erik Seligman

    Erik Seligman
    Erik is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the “Math Mutation” podcast, and has served as an elected director on the Hillsboro school board.

    Affiliations and Expertise

    Cadence Design Systems, working with the Jasper Formal Verification tool suite.

    Tom Schubert

    Tom is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis.

    Affiliations and Expertise

    Formerly at Intel, now directing the ECE graduate track in Design Verification and Validation at Portland State University, Portland, Oregon.

    M V Achutha Kiran Kumar

    Kiran is a Senior Principal Engineer at intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 18 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification..

    Affiliations and Expertise

    Formal Verification Central Technology Office, Intel, India

    Latest reviews

    (Total rating for all reviews)

    • Carlos C. Fri Nov 26 2021

      Book well structure

      It is easy to read with clear and practical examples. It is well structure to acquire knowledge each Chapters. Brings you to a good level of Forma Verification.

    • Ben C. Wed Aug 11 2021

      Excellent book for engineers using formal verification and/or simulation

      Aside from addressing the topic of formal verification with SVA with great depths, I strongly encourage the reading of this book by RTL designers and verification engineers who use formal or simulation.  This book shows a lot of maturity and knowledge from the authors, and this experience is clearly demonstrated with the multitude of examples and advice, tips, and things to watch out when addressing verification with SVA for formal and for simulation. The book is well organized and presented.

    • JYOTI M. Mon Nov 05 2018

      Nice Explanation

      Easy to understand the concept of Formal Verification..