Electronic Design Automation

1st Edition

Synthesis, Verification, and Test

Editors: Laung-Terng Wang Yao-Wen Chang Kwang-Ting (Tim) Cheng
Hardcover ISBN: 9780123743640
eBook ISBN: 9780080922003
Imprint: Morgan Kaufmann
Published Date: 26th February 2009
Page Count: 972
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Table of Contents

Chapter 1: Introduction
Chapter 2: Fundamentals of CMOS Design
Chapter 3: Design for Testability
Chapter 4: Fundamentals of Algorithms
Chapter 5: Electronic System-Level Design and High-Level Synthesis
Chapter 6: Logic Synthesis in a Nutshell
Chapter 7: Test Synthesis
Chapter 8: Logic and Circuit Simulation
Chapter 9: Functional Verification
Chapter 10: Floorplanning
Chapter 11: Placement
Chapter 12: Global and Detailed Routing
Chapter 13: Synthesis of Clock and Power/Ground Networks
Chapter 14: Fault Simulation and Test Generation.


Description

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.

Key Features

  • Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
  • Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
  • Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
  • Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes

Readership

Practitioners/Researchers in electronic design automation, including VLSI design engineers, verfication engineers, and test engineers.


Details

No. of pages:
972
Language:
English
Copyright:
© Morgan Kaufmann 2009
Published:
Imprint:
Morgan Kaufmann
eBook ISBN:
9780080922003
Hardcover ISBN:
9780123743640

About the Editors

Laung-Terng Wang Editor

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Affiliations and Expertise

SynTest Technologies, Inc., Sunnyvale, CA, USA

Yao-Wen Chang Editor

Yao-Wen Chang, Ph.D., is a Professor in the Department of Electrical Engineering, National Taiwan University. He recevied his Ph.D. degree in Computer Science from the University of Texas at Austin. He has published over 200 technical papers, co-authored one book, and is a winner of the ACM ISPD Placement (2006) and Global Routing (2008) contests.

Affiliations and Expertise

National Taiwan University, Taipai, Taiwan

Kwang-Ting (Tim) Cheng Editor

Kwang-Ting (Tim) Cheng, Ph.D., is a Professor and Chair of the Electrical and Computer Engineering Department at the University of California, Berkeley. A Fellow of the IEEE, he has published over 300 technical papers, co-authored three books, and holds 11 U.S. Patents.

Affiliations and Expertise

University of California, Santa Barbara, USA